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@@ -603,6 +603,10 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
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? RADEON_CRTC2_INTERLACE_EN
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: 0));
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+ /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
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+ if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
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+ crtc2_gen_cntl |= RADEON_CRTC2_EN;
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+
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disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
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disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
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@@ -630,6 +634,10 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
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? RADEON_CRTC_INTERLACE_EN
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: 0));
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+ /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
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+ if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
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+ crtc_gen_cntl |= RADEON_CRTC_EN;
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+
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crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
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crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
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RADEON_CRTC_VSYNC_DIS |
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