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@@ -16,6 +16,58 @@
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#include <asm/tlbflush.h>
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#include <asm/tlbflush.h>
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#ifdef CONFIG_CPU_CACHE_VIPT
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#ifdef CONFIG_CPU_CACHE_VIPT
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+
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+void flush_cache_mm(struct mm_struct *mm)
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+{
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+ if (cache_is_vivt()) {
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+ if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
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+ __cpuc_flush_user_all();
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+ return;
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+ }
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+
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+ if (cache_is_vipt_aliasing()) {
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+ asm( "mcr p15, 0, %0, c7, c14, 0\n"
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+ " mcr p15, 0, %0, c7, c5, 0\n"
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+ " mcr p15, 0, %0, c7, c10, 4"
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+ :
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+ : "r" (0)
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+ : "cc");
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+ }
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+}
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+
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+void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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+{
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+ if (cache_is_vivt()) {
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+ if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
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+ __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
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+ vma->vm_flags);
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+ return;
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+ }
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+
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+ if (cache_is_vipt_aliasing()) {
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+ asm( "mcr p15, 0, %0, c7, c14, 0\n"
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+ " mcr p15, 0, %0, c7, c5, 0\n"
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+ " mcr p15, 0, %0, c7, c10, 4"
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+ :
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+ : "r" (0)
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+ : "cc");
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+ }
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+}
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+
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+void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
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+{
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+ if (cache_is_vivt()) {
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+ if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
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+ unsigned long addr = user_addr & PAGE_MASK;
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+ __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
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+ }
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+ return;
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+ }
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+
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+ if (cache_is_vipt_aliasing())
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+ flush_pfn_alias(pfn, user_addr);
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+}
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+
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#define ALIAS_FLUSH_START 0xffff4000
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#define ALIAS_FLUSH_START 0xffff4000
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#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
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#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
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