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@@ -49,6 +49,8 @@
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/* #define USE_KMALLOC */
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+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+
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#include "mite.h"
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#include "comedi_fc.h"
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@@ -75,7 +77,7 @@ static void mite_init(void)
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mite = kzalloc(sizeof(*mite), GFP_KERNEL);
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if (!mite) {
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- printk(KERN_ERR "mite: allocation failed\n");
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+ pr_err("allocation failed\n");
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pci_dev_put(pcidev);
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return;
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}
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@@ -94,14 +96,12 @@ static void mite_init(void)
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static void dump_chip_signature(u32 csigr_bits)
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{
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- printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
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- "interface mode = %i\n",
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- mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
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- mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
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- printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
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- "wins = %i, iowins = %i\n",
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- mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
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- mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
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+ pr_info("version = %i, type = %i, mite mode = %i, interface mode = %i\n",
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+ mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
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+ mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
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+ pr_info("num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
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+ mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
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+ mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
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}
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unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
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@@ -121,7 +121,8 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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unsigned unknown_dma_burst_bits;
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if (comedi_pci_enable(mite->pcidev, "mite")) {
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- printk(KERN_ERR "error enabling mite and requesting io regions\n");
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+ dev_err(&mite->pcidev->dev,
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+ "error enabling mite and requesting io regions\n");
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return -EIO;
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}
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pci_set_master(mite->pcidev);
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@@ -130,11 +131,10 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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mite->mite_phys_addr = addr;
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mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
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if (!mite->mite_io_addr) {
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- printk(KERN_ERR "Failed to remap mite io memory address\n");
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+ dev_err(&mite->pcidev->dev,
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+ "Failed to remap mite io memory address\n");
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return -ENOMEM;
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}
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- printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
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- (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
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addr = pci_resource_start(mite->pcidev, 1);
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mite->daq_phys_addr = addr;
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@@ -145,15 +145,15 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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*/
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mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
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if (!mite->daq_io_addr) {
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- printk(KERN_ERR "Failed to remap daq io memory address\n");
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+ dev_err(&mite->pcidev->dev,
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+ "Failed to remap daq io memory address\n");
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return -ENOMEM;
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}
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- printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
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- (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
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if (use_iodwbsr_1) {
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writel(0, mite->mite_io_addr + MITE_IODWBSR);
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- printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
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+ dev_info(&mite->pcidev->dev,
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+ "using I/O Window Base Size register 1\n");
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writel(mite->daq_phys_addr | WENAB |
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MITE_IODWBSR_1_WSIZE_bits(length),
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mite->mite_io_addr + MITE_IODWBSR_1);
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@@ -178,9 +178,9 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
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mite->num_channels = mite_csigr_dmac(csigr_bits);
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if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
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- printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
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- "channels. Setting to %i.\n",
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- mite->num_channels, MAX_MITE_DMA_CHANNELS);
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+ dev_warn(&mite->pcidev->dev,
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+ "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
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+ mite->num_channels, MAX_MITE_DMA_CHANNELS);
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mite->num_channels = MAX_MITE_DMA_CHANNELS;
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}
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dump_chip_signature(csigr_bits);
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@@ -193,7 +193,7 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
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mite->mite_io_addr + MITE_CHCR(i));
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}
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mite->fifo_size = mite_fifo_size(mite, 0);
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- printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
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+ dev_info(&mite->pcidev->dev, "fifo size is %i.\n", mite->fifo_size);
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mite->used = 1;
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return 0;
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@@ -245,15 +245,13 @@ void mite_list_devices(void)
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{
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struct mite_struct *mite, *next;
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- printk(KERN_INFO "Available NI device IDs:");
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+ pr_info("Available NI device IDs:\n");
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if (mite_devices)
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for (mite = mite_devices; mite; mite = next) {
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next = mite->next;
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- printk(KERN_INFO " 0x%04x", mite_device_id(mite));
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- if (mite->used)
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- printk(KERN_INFO "(used)");
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+ pr_info("0x%04x%s\n", mite_device_id(mite),
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+ mite->used ? " (used)" : "");
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}
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- printk(KERN_INFO "\n");
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}
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EXPORT_SYMBOL(mite_list_devices);
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@@ -352,7 +350,7 @@ void mite_dma_arm(struct mite_channel *mite_chan)
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int chor;
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unsigned long flags;
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- MDPRINTK("mite_dma_arm ch%i\n", channel);
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+ MDPRINTK("mite_dma_arm ch%i\n", mite_chan->channel);
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/*
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* memory barrier is intended to insure any twiddling with the buffer
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* is done before writing to the mite to arm dma transfer
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@@ -400,7 +398,8 @@ int mite_buf_change(struct mite_dma_descriptor_ring *ring,
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n_links * sizeof(struct mite_dma_descriptor),
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&ring->descriptors_dma_addr, GFP_KERNEL);
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if (!ring->descriptors) {
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- printk(KERN_ERR "mite: ring buffer allocation failed\n");
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+ dev_err(async->subdevice->device->class_dev,
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+ "mite: ring buffer allocation failed\n");
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return -ENOMEM;
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}
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ring->n_links = n_links;
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@@ -477,8 +476,7 @@ void mite_prep_dma(struct mite_channel *mite_chan,
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mcr |= CR_PSIZE32;
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break;
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default:
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- printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
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- "transfer\n");
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+ pr_warn("bug! invalid mem bit width for dma transfer\n");
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break;
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}
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writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
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@@ -497,8 +495,7 @@ void mite_prep_dma(struct mite_channel *mite_chan,
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dcr |= CR_PSIZE32;
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break;
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default:
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- printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
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- "transfer\n");
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+ pr_warn("bug! invalid dev bit width for dma transfer\n");
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break;
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}
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writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
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@@ -612,7 +609,8 @@ int mite_sync_input_dma(struct mite_channel *mite_chan,
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nbytes = mite_bytes_written_to_memory_lb(mite_chan);
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if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
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old_alloc_count) > 0) {
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- printk("mite: DMA overwrite of free area\n");
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+ dev_warn(async->subdevice->device->class_dev,
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+ "mite: DMA overwrite of free area\n");
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async->events |= COMEDI_CB_OVERFLOW;
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return -1;
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}
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@@ -656,7 +654,8 @@ int mite_sync_output_dma(struct mite_channel *mite_chan,
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(int)(nbytes_ub - stop_count) > 0)
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nbytes_ub = stop_count;
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if ((int)(nbytes_ub - old_alloc_count) > 0) {
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- printk(KERN_ERR "mite: DMA underrun\n");
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+ dev_warn(async->subdevice->device->class_dev,
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+ "mite: DMA underrun\n");
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async->events |= COMEDI_CB_OVERFLOW;
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return -1;
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}
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@@ -707,8 +706,6 @@ EXPORT_SYMBOL(mite_done);
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#ifdef DEBUG_MITE
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-static void mite_decode(char **bit_str, unsigned int bits);
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-
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/* names of bits in mite registers */
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static const char *const mite_CHOR_strings[] = {
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@@ -778,70 +775,67 @@ static const char *const mite_CHSR_strings[] = {
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"28", "lpauses", "30", "int",
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};
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-void mite_dump_regs(struct mite_channel *mite_chan)
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-{
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- unsigned long mite_io_addr =
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- (unsigned long)mite_chan->mite->mite_io_addr;
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- unsigned long addr = 0;
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- unsigned long temp = 0;
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-
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- printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
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- printk(KERN_DEBUG "mite address is =0x%08lx\n", mite_io_addr);
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-
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- addr = mite_io_addr + MITE_CHOR(channel);
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- printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
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- temp = readl(addr));
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- mite_decode(mite_CHOR_strings, temp);
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- addr = mite_io_addr + MITE_CHCR(channel);
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- printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
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- temp = readl(addr));
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- mite_decode(mite_CHCR_strings, temp);
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- addr = mite_io_addr + MITE_TCR(channel);
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- printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
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- readl(addr));
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- addr = mite_io_addr + MITE_MCR(channel);
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- printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
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- temp = readl(addr));
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- mite_decode(mite_MCR_strings, temp);
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-
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- addr = mite_io_addr + MITE_MAR(channel);
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- printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
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- readl(addr));
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- addr = mite_io_addr + MITE_DCR(channel);
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- printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
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- temp = readl(addr));
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- mite_decode(mite_DCR_strings, temp);
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- addr = mite_io_addr + MITE_DAR(channel);
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- printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
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- readl(addr));
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- addr = mite_io_addr + MITE_LKCR(channel);
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- printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
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- temp = readl(addr));
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- mite_decode(mite_LKCR_strings, temp);
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- addr = mite_io_addr + MITE_LKAR(channel);
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- printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
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- readl(addr));
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- addr = mite_io_addr + MITE_CHSR(channel);
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- printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
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- temp = readl(addr));
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- mite_decode(mite_CHSR_strings, temp);
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- addr = mite_io_addr + MITE_FCR(channel);
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- printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
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- readl(addr));
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-}
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-EXPORT_SYMBOL(mite_dump_regs);
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-
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-static void mite_decode(char **bit_str, unsigned int bits)
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+static void mite_decode(const char *const *bit_str, unsigned int bits)
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{
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int i;
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for (i = 31; i >= 0; i--) {
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if (bits & (1 << i))
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- printk(KERN_DEBUG " %s", bit_str[i]);
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+ pr_debug(" %s\n", bit_str[i]);
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}
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- printk(KERN_DEBUG "\n");
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}
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-EXPORT_SYMBOL(mite_decode);
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+
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+void mite_dump_regs(struct mite_channel *mite_chan)
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+{
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+ void __iomem *mite_io_addr = mite_chan->mite->mite_io_addr;
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+ unsigned int offset;
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+ unsigned int value;
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+ int channel = mite_chan->channel;
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+
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+ pr_debug("mite_dump_regs ch%i\n", channel);
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+ pr_debug("mite address is =%p\n", mite_io_addr);
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+
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+ offset = MITE_CHOR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[CHOR] at 0x%08x =0x%08x\n", offset, value);
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+ mite_decode(mite_CHOR_strings, value);
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+ offset = MITE_CHCR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[CHCR] at 0x%08x =0x%08x\n", offset, value);
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+ mite_decode(mite_CHCR_strings, value);
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+ offset = MITE_TCR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[TCR] at 0x%08x =0x%08x\n", offset, value);
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+ offset = MITE_MCR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[MCR] at 0x%08x =0x%08x\n", offset, value);
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+ mite_decode(mite_MCR_strings, value);
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+ offset = MITE_MAR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[MAR] at 0x%08x =0x%08x\n", offset, value);
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+ offset = MITE_DCR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[DCR] at 0x%08x =0x%08x\n", offset, value);
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+ mite_decode(mite_DCR_strings, value);
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+ offset = MITE_DAR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[DAR] at 0x%08x =0x%08x\n", offset, value);
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+ offset = MITE_LKCR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[LKCR] at 0x%08x =0x%08x\n", offset, value);
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+ mite_decode(mite_LKCR_strings, value);
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+ offset = MITE_LKAR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[LKAR] at 0x%08x =0x%08x\n", offset, value);
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+ offset = MITE_CHSR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[CHSR] at 0x%08x =0x%08x\n", offset, value);
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+ mite_decode(mite_CHSR_strings, value);
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+ offset = MITE_FCR(channel);
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+ value = readl(mite_io_addr + offset);
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+ pr_debug("mite status[FCR] at 0x%08x =0x%08x\n", offset, value);
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+}
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+EXPORT_SYMBOL(mite_dump_regs);
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#endif
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#ifdef MODULE
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