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@@ -111,6 +111,7 @@ static void __init rbtx4938_pci_setup(void)
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#define SEEPROM2_CS 0 /* IOC */
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#define SEEPROM2_CS 0 /* IOC */
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#define SEEPROM3_CS 1 /* IOC */
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#define SEEPROM3_CS 1 /* IOC */
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#define SRTC_CS 2 /* IOC */
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#define SRTC_CS 2 /* IOC */
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+#define SPI_BUSNO 0
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static int __init rbtx4938_ethaddr_init(void)
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static int __init rbtx4938_ethaddr_init(void)
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{
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{
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@@ -120,7 +121,7 @@ static int __init rbtx4938_ethaddr_init(void)
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int i;
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int i;
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/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
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/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
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- if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
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+ if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
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printk(KERN_ERR "seeprom: read error.\n");
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printk(KERN_ERR "seeprom: read error.\n");
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return -ENODEV;
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return -ENODEV;
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} else {
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} else {
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@@ -287,9 +288,9 @@ static int __init rbtx4938_spi_init(void)
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.mode = SPI_MODE_1 | SPI_CS_HIGH,
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.mode = SPI_MODE_1 | SPI_CS_HIGH,
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};
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};
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spi_register_board_info(&srtc_info, 1);
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spi_register_board_info(&srtc_info, 1);
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- spi_eeprom_register(SEEPROM1_CS);
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- spi_eeprom_register(16 + SEEPROM2_CS);
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- spi_eeprom_register(16 + SEEPROM3_CS);
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+ spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
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+ spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
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+ spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
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gpio_request(16 + SRTC_CS, "rtc-rs5c348");
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gpio_request(16 + SRTC_CS, "rtc-rs5c348");
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gpio_direction_output(16 + SRTC_CS, 0);
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gpio_direction_output(16 + SRTC_CS, 0);
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gpio_request(SEEPROM1_CS, "seeprom1");
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gpio_request(SEEPROM1_CS, "seeprom1");
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@@ -298,7 +299,7 @@ static int __init rbtx4938_spi_init(void)
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gpio_direction_output(16 + SEEPROM2_CS, 1);
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gpio_direction_output(16 + SEEPROM2_CS, 1);
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gpio_request(16 + SEEPROM3_CS, "seeprom3");
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gpio_request(16 + SEEPROM3_CS, "seeprom3");
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gpio_direction_output(16 + SEEPROM3_CS, 1);
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gpio_direction_output(16 + SEEPROM3_CS, 1);
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- tx4938_spi_init(0);
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+ tx4938_spi_init(SPI_BUSNO);
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return 0;
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return 0;
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}
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}
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