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@@ -511,3 +511,31 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size);
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+
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+/*
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+ * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
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+ * confusing the PCI engine:
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+ */
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+static void sb600_disable_hpet_bar(struct pci_dev *dev)
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+{
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+ u8 val;
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+
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+ /*
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+ * The SB600 and SB700 both share the same device
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+ * ID, but the PM register 0x55 does something different
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+ * for the SB700, so make sure we are dealing with the
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+ * SB600 before touching the bit:
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+ */
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+
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+ pci_read_config_byte(dev, 0x08, &val);
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+
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+ if (val < 0x2F) {
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+ outb(0x55, 0xCD6);
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+ val = inb(0xCD7);
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+
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+ /* Set bit 7 in PM register 0x55 */
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+ outb(0x55, 0xCD6);
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+ outb(val | 0x80, 0xCD7);
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+ }
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
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