Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (50 commits)
  [MIPS] Add smp_call_function_single()
  [MIPS] thread_info.h: kmalloc + memset conversion to kzalloc
  [MIPS] Kexec: Fix several 64-bit bugs.
  [MIPS] Kexec: Fix several warnings.
  [MIPS] DDB5477: Remove support
  [MIPS] Fulong: Remove unneeded header file
  [MIPS] Cobalt: Enable UART on RaQ1
  [MIPS] Remove unused GROUP_TOSHIBA_NAMES
  [MIPS] remove some duplicate includes
  [MIPS] Oprofile: Fix rm9000 performance counter handler
  [MIPS] Use -Werror on subdirectories which build cleanly.
  [MIPS] Yosemite: Fix warning.
  [MIPS] PMON: Fix cpustart declaration.
  [MIPS] Yosemite: Only build ll_ht_smp_irq_handler() if HYPERTRANSPORT.
  [MIPS] Yosemite: Fix build error due to undeclared titan_mailbox_irq().
  [MIPS] Yosemite: Don't declare titan_mailbox_irq() as asmlinkage.
  [MIPS] Yosemite: Fix warnings in i2c-yoesmite by deleting the unused code.
  [MIPS] Delete unused arch/mips/gt64120/common/
  [MIPS] Fix build warning in unaligned load/store emulator.
  [MIPS] IP32: Don't ignore request_irq's return value.
  ...

arch/mips/Kconfig

@@ -15,29 +15,6 @@ choice
 	prompt "System type"
 	default SGI_IP22
 
-config LEMOTE_FULONG
-	bool "Lemote Fulong mini-PC"
-	select ARCH_SPARSEMEM_ENABLE
-	select SYS_HAS_CPU_LOONGSON2
-	select DMA_NONCOHERENT
-	select BOOT_ELF32
-	select BOARD_SCACHE
-	select HAVE_STD_PC_SERIAL_PORT
-	select HW_HAS_PCI
-	select I8259
-	select ISA
-	select IRQ_CPU
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select SYS_SUPPORTS_64BIT_KERNEL
-	select SYS_SUPPORTS_LITTLE_ENDIAN
-	select SYS_SUPPORTS_HIGHMEM
-	select SYS_HAS_EARLY_PRINTK
-	select GENERIC_HARDIRQS_NO__DO_IRQ
-	select CPU_HAS_WB
-	help
-	  Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
-	  an FPGA northbridge
-
 config MACH_ALCHEMY
 	bool "Alchemy processor based machines"
 
@@ -131,6 +108,29 @@ config MACH_JAZZ
 	 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
 	 Olivetti M700-10 workstations.
 
+config LEMOTE_FULONG
+	bool "Lemote Fulong mini-PC"
+	select ARCH_SPARSEMEM_ENABLE
+	select SYS_HAS_CPU_LOONGSON2
+	select DMA_NONCOHERENT
+	select BOOT_ELF32
+	select BOARD_SCACHE
+	select HAVE_STD_PC_SERIAL_PORT
+	select HW_HAS_PCI
+	select I8259
+	select ISA
+	select IRQ_CPU
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_HAS_EARLY_PRINTK
+	select GENERIC_HARDIRQS_NO__DO_IRQ
+	select CPU_HAS_WB
+	help
+	  Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
+	  an FPGA northbridge
+
 config MIPS_ATLAS
 	bool "MIPS Atlas board"
 	select BOOT_ELF32
@@ -210,27 +210,6 @@ config MIPS_SEAD
 	  This enables support for the MIPS Technologies SEAD evaluation
 	  board.
 
-config WR_PPMC
-	bool "Wind River PPMC board"
-	select IRQ_CPU
-	select BOOT_ELF32
-	select DMA_NONCOHERENT
-	select HW_HAS_PCI
-	select PCI_GT64XXX_PCI0
-	select SWAP_IO_SPACE
-	select SYS_HAS_CPU_MIPS32_R1
-	select SYS_HAS_CPU_MIPS32_R2
-	select SYS_HAS_CPU_MIPS64_R1
-	select SYS_HAS_CPU_NEVADA
-	select SYS_HAS_CPU_RM7000
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select SYS_SUPPORTS_64BIT_KERNEL
-	select SYS_SUPPORTS_BIG_ENDIAN
-	select SYS_SUPPORTS_LITTLE_ENDIAN
-	help
-	  This enables support for the Wind River MIPS32 4KC PPMC evaluation
-	  board, which is based on GT64120 bridge chip.
-
 config MIPS_SIM
 	bool 'MIPS simulator (MIPSsim)'
 	select DMA_NONCOHERENT
@@ -248,23 +227,24 @@ config MIPS_SIM
 	  This option enables support for MIPS Technologies MIPSsim software
 	  emulator.
 
-config MOMENCO_OCELOT
-	bool "Momentum Ocelot board"
+config MARKEINS
+	bool "NEC EMMA2RH Mark-eins"
 	select DMA_NONCOHERENT
 	select HW_HAS_PCI
 	select IRQ_CPU
-	select IRQ_CPU_RM7K
-	select PCI_GT64XXX_PCI0
-	select RM7000_CPU_SCACHE
 	select SWAP_IO_SPACE
-	select SYS_HAS_CPU_RM7000
 	select SYS_SUPPORTS_32BIT_KERNEL
-	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
-	select SYS_SUPPORTS_KGDB
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_HAS_CPU_R5000
 	help
-	  The Ocelot is a MIPS-based Single Board Computer (SBC) made by
-	  Momentum Computer <http://www.momenco.com/>.
+	  This enables support for the R5432-based NEC Mark-eins
+	  boards with R5500 CPU.
+
+config MACH_VR41XX
+	bool "NEC VR4100 series based machines"
+	select SYS_HAS_CPU_VR41XX
+	select GENERIC_HARDIRQS_NO__DO_IRQ
 
 config PNX8550_JBS
 	bool "Philips PNX8550 based JBS board"
@@ -276,31 +256,6 @@ config PNX8550_STB810
 	select PNX8550
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config DDB5477
-	bool "NEC DDB Vrc-5477"
-	select DDB5XXX_COMMON
-	select DMA_NONCOHERENT
-	select HW_HAS_PCI
-	select I8259
-	select IRQ_CPU
-	select SYS_HAS_CPU_R5432
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-	select SYS_SUPPORTS_KGDB
-	select SYS_SUPPORTS_KGDB
-	select SYS_SUPPORTS_LITTLE_ENDIAN
-	help
-	  This enables support for the R5432-based NEC DDB Vrc-5477,
-	  or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
-
-	  Features : kernel debugging, serial terminal, NFS root fs, on-board
-	  ether port USB, AC97, PCI, etc.
-
-config MACH_VR41XX
-	bool "NEC VR4100 series based machines"
-	select SYS_HAS_CPU_VR41XX
-	select GENERIC_HARDIRQS_NO__DO_IRQ
-
 config PMC_MSP
 	bool "PMC-Sierra MSP chipsets"
 	depends on EXPERIMENTAL
@@ -367,20 +322,6 @@ config QEMU
 	  simulate actual MIPS hardware platforms.  More information on Qemu
 	  can be found at http://www.linux-mips.org/wiki/Qemu.
 
-config MARKEINS
-	bool "NEC EMMA2RH Mark-eins"
-	select DMA_NONCOHERENT
-	select HW_HAS_PCI
-	select IRQ_CPU
-	select SWAP_IO_SPACE
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select SYS_SUPPORTS_BIG_ENDIAN
-	select SYS_SUPPORTS_LITTLE_ENDIAN
-	select SYS_HAS_CPU_R5000
-	help
-	  This enables support for the R5432-based NEC Mark-eins
-	  boards with R5500 CPU.
-
 config SGI_IP22
 	bool "SGI IP22 (Indy/Indigo2)"
 	select ARC
@@ -443,41 +384,38 @@ config SGI_IP32
 	help
 	  If you want this kernel to run on SGI O2 workstation, say Y here.
 
-config SIBYTE_BIGSUR
-	bool "Sibyte BCM91480B-BigSur"
+config SIBYTE_CRHINE
+	bool "Sibyte BCM91120C-CRhine"
+	depends on EXPERIMENTAL
 	select BOOT_ELF32
 	select DMA_COHERENT
-	select NR_CPUS_DEFAULT_4
-	select PCI_DOMAINS
-	select SIBYTE_BCM1x80
+	select SIBYTE_BCM1120
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config SIBYTE_SWARM
-	bool "Sibyte BCM91250A-SWARM"
+config SIBYTE_CARMEL
+	bool "Sibyte BCM91120x-Carmel"
+	depends on EXPERIMENTAL
 	select BOOT_ELF32
 	select DMA_COHERENT
-	select NR_CPUS_DEFAULT_2
-	select SIBYTE_SB1250
+	select SIBYTE_BCM1120
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1
 	select SYS_SUPPORTS_BIG_ENDIAN
-	select SYS_SUPPORTS_HIGHMEM
-	select SYS_SUPPORTS_KGDB
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config SIBYTE_SENTOSA
-	bool "Sibyte BCM91250E-Sentosa"
+config SIBYTE_CRHONE
+	bool "Sibyte BCM91125C-CRhone"
 	depends on EXPERIMENTAL
 	select BOOT_ELF32
 	select DMA_COHERENT
-	select NR_CPUS_DEFAULT_2
-	select SIBYTE_SB1250
+	select SIBYTE_BCM1125
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1
 	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_RHONE
@@ -491,19 +429,21 @@ config SIBYTE_RHONE
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config SIBYTE_CARMEL
-	bool "Sibyte BCM91120x-Carmel"
-	depends on EXPERIMENTAL
+config SIBYTE_SWARM
+	bool "Sibyte BCM91250A-SWARM"
 	select BOOT_ELF32
 	select DMA_COHERENT
-	select SIBYTE_BCM1120
+	select NR_CPUS_DEFAULT_2
+	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1
 	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_SUPPORTS_KGDB
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config SIBYTE_PTSWARM
-	bool "Sibyte BCM91250PT-PTSWARM"
+config SIBYTE_LITTLESUR
+	bool "Sibyte BCM91250C2-LittleSur"
 	depends on EXPERIMENTAL
 	select BOOT_ELF32
 	select DMA_COHERENT
@@ -515,8 +455,8 @@ config SIBYTE_PTSWARM
 	select SYS_SUPPORTS_HIGHMEM
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config SIBYTE_LITTLESUR
-	bool "Sibyte BCM91250C2-LittleSur"
+config SIBYTE_SENTOSA
+	bool "Sibyte BCM91250E-Sentosa"
 	depends on EXPERIMENTAL
 	select BOOT_ELF32
 	select DMA_COHERENT
@@ -525,30 +465,31 @@ config SIBYTE_LITTLESUR
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1
 	select SYS_SUPPORTS_BIG_ENDIAN
-	select SYS_SUPPORTS_HIGHMEM
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config SIBYTE_CRHINE
-	bool "Sibyte BCM91120C-CRhine"
+config SIBYTE_PTSWARM
+	bool "Sibyte BCM91250PT-PTSWARM"
 	depends on EXPERIMENTAL
 	select BOOT_ELF32
 	select DMA_COHERENT
-	select SIBYTE_BCM1120
+	select NR_CPUS_DEFAULT_2
+	select SIBYTE_SB1250
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1
 	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
-config SIBYTE_CRHONE
-	bool "Sibyte BCM91125C-CRhone"
-	depends on EXPERIMENTAL
+config SIBYTE_BIGSUR
+	bool "Sibyte BCM91480B-BigSur"
 	select BOOT_ELF32
 	select DMA_COHERENT
-	select SIBYTE_BCM1125
+	select NR_CPUS_DEFAULT_4
+	select PCI_DOMAINS
+	select SIBYTE_BCM1x80
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_SB1
 	select SYS_SUPPORTS_BIG_ENDIAN
-	select SYS_SUPPORTS_HIGHMEM
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SNI_RM
@@ -595,7 +536,7 @@ config TOSHIBA_JMR3927
 	select GENERIC_HARDIRQS_NO__DO_IRQ
 
 config TOSHIBA_RBTX4927
-	bool "Toshiba TBTX49[23]7 board"
+	bool "Toshiba RBTX49[23]7 board"
 	select DMA_NONCOHERENT
 	select HAS_TXX9_SERIAL
 	select HW_HAS_PCI
@@ -632,10 +573,30 @@ config TOSHIBA_RBTX4938
 	  This Toshiba board is based on the TX4938 processor. Say Y here to
 	  support this machine type
 
+config WR_PPMC
+	bool "Wind River PPMC board"
+	select IRQ_CPU
+	select BOOT_ELF32
+	select DMA_NONCOHERENT
+	select HW_HAS_PCI
+	select PCI_GT64XXX_PCI0
+	select SWAP_IO_SPACE
+	select SYS_HAS_CPU_MIPS32_R1
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_HAS_CPU_MIPS64_R1
+	select SYS_HAS_CPU_NEVADA
+	select SYS_HAS_CPU_RM7000
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	help
+	  This enables support for the Wind River MIPS32 4KC PPMC evaluation
+	  board, which is based on GT64120 bridge chip.
+
 endchoice
 
 source "arch/mips/au1000/Kconfig"
-source "arch/mips/ddb5xxx/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
 source "arch/mips/sgi-ip27/Kconfig"
@@ -807,10 +768,6 @@ config IRQ_MSP_SLP
 config IRQ_MSP_CIC
 	bool
 
-config DDB5XXX_COMMON
-	bool
-	select SYS_SUPPORTS_KGDB
-
 config MIPS_BOARDS_GEN
 	bool
 
@@ -1377,17 +1334,6 @@ config MIPS_MT_SMTC
 	  This is a kernel model which is known a SMTC or lately has been
 	  marketesed into SMVP.
 
-config MIPS_VPE_LOADER
-	bool "VPE loader support."
-	depends on SYS_SUPPORTS_MULTITHREADING
-	select CPU_MIPSR2_IRQ_VI
-	select CPU_MIPSR2_IRQ_EI
-	select CPU_MIPSR2_SRS
-	select MIPS_MT
-	help
-	  Includes a loader for loading an elf relocatable object
-	  onto another VPE and running it.
-
 endchoice
 
 config MIPS_MT
@@ -1398,8 +1344,19 @@ config SYS_SUPPORTS_MULTITHREADING
 
 config MIPS_MT_FPAFF
 	bool "Dynamic FPU affinity for FP-intensive threads"
-	depends on MIPS_MT
 	default y
+	depends on MIPS_MT_SMP || MIPS_MT_SMTC
+
+config MIPS_VPE_LOADER
+	bool "VPE loader support."
+	depends on SYS_SUPPORTS_MULTITHREADING
+	select CPU_MIPSR2_IRQ_VI
+	select CPU_MIPSR2_IRQ_EI
+	select CPU_MIPSR2_SRS
+	select MIPS_MT
+	help
+	  Includes a loader for loading an elf relocatable object
+	  onto another VPE and running it.
 
 config MIPS_MT_SMTC_INSTANT_REPLAY
 	bool "Low-latency Dispatch of Deferred SMTC IPIs"
@@ -1772,7 +1729,7 @@ config KEXEC
 
 config SECCOMP
 	bool "Enable seccomp to safely compute untrusted bytecode"
-	depends on PROC_FS && BROKEN
+	depends on PROC_FS
 	default y
 	help
 	  This kernel feature is useful for number crunching applications

arch/mips/Makefile

@@ -67,6 +67,8 @@ cflags-y		+= $(call cc-option,-msym32)
 endif
 endif
 
+all-$(CONFIG_BOOT_ELF32)	:= $(vmlinux-32)
+all-$(CONFIG_BOOT_ELF64)	:= $(vmlinux-64)
 
 #
 # GCC uses -G 0 -mabicalls -fpic as default.  We don't want PIC in the kernel
@@ -309,6 +311,7 @@ core-$(CONFIG_MIPS_ATLAS)	+= arch/mips/mips-boards/atlas/
 cflags-$(CONFIG_MIPS_ATLAS)	+= -Iinclude/asm-mips/mach-atlas
 cflags-$(CONFIG_MIPS_ATLAS)	+= -Iinclude/asm-mips/mach-mips
 load-$(CONFIG_MIPS_ATLAS)	+= 0xffffffff80100000
+all-$(CONFIG_MIPS_ATLAS)	:= vmlinux.srec
 
 #
 # MIPS Malta board
@@ -316,6 +319,7 @@ load-$(CONFIG_MIPS_ATLAS)	+= 0xffffffff80100000
 core-$(CONFIG_MIPS_MALTA)	+= arch/mips/mips-boards/malta/
 cflags-$(CONFIG_MIPS_MALTA)	+= -Iinclude/asm-mips/mach-mips
 load-$(CONFIG_MIPS_MALTA)	+= 0xffffffff80100000
+all-$(CONFIG_MIPS_MALTA)	:= vmlinux.srec
 
 #
 # MIPS SEAD board
@@ -323,6 +327,7 @@ load-$(CONFIG_MIPS_MALTA)	+= 0xffffffff80100000
 core-$(CONFIG_MIPS_SEAD)	+= arch/mips/mips-boards/sead/
 cflags-$(CONFIG_MIPS_SEAD)	+= -Iinclude/asm-mips/mach-mips
 load-$(CONFIG_MIPS_SEAD)	+= 0xffffffff80100000
+all-$(CONFIG_MIPS_SEAD)		:= vmlinux.srec
 
 #
 # MIPS SIM
@@ -331,17 +336,6 @@ core-$(CONFIG_MIPS_SIM)		+= arch/mips/mipssim/
 cflags-$(CONFIG_MIPS_SIM)	+= -Iinclude/asm-mips/mach-mipssim
 load-$(CONFIG_MIPS_SIM)		+= 0x80100000
 
-#
-# Momentum Ocelot board
-#
-# The Ocelot setup.o must be linked early - it does the ioremap() for the
-# mips_io_port_base.
-#
-core-$(CONFIG_MOMENCO_OCELOT)	+= arch/mips/gt64120/common/ \
-				   arch/mips/gt64120/momenco_ocelot/
-cflags-$(CONFIG_MOMENCO_OCELOT)	+= -Iinclude/asm-mips/mach-ocelot
-load-$(CONFIG_MOMENCO_OCELOT)	+= 0xffffffff80100000
-
 #
 # PMC-Sierra MSP SOCs
 #
@@ -363,6 +357,7 @@ load-$(CONFIG_PMC_YOSEMITE)	+= 0xffffffff80100000
 core-$(CONFIG_QEMU)		+= arch/mips/qemu/
 cflags-$(CONFIG_QEMU)		+= -Iinclude/asm-mips/mach-qemu
 load-$(CONFIG_QEMU)		+= 0xffffffff80010000
+all-$(CONFIG_QEMU)		:= vmlinux.bin
 
 #
 # Basler eXcite
@@ -371,17 +366,6 @@ core-$(CONFIG_BASLER_EXCITE)	+= arch/mips/basler/excite/
 cflags-$(CONFIG_BASLER_EXCITE)	+= -Iinclude/asm-mips/mach-excite
 load-$(CONFIG_BASLER_EXCITE)	+= 0x80100000
 
-#
-# NEC DDB
-#
-core-$(CONFIG_DDB5XXX_COMMON)	+= arch/mips/ddb5xxx/common/
-
-#
-# NEC DDB Vrc-5477
-#
-core-$(CONFIG_DDB5477)		+= arch/mips/ddb5xxx/ddb5477/
-load-$(CONFIG_DDB5477)		+= 0xffffffff80100000
-
 #
 # Common VR41xx
 #
@@ -554,6 +538,7 @@ load-$(CONFIG_SIBYTE_BIGSUR)	:= 0xffffffff80100000
 core-$(CONFIG_SNI_RM)		+= arch/mips/sni/
 cflags-$(CONFIG_SNI_RM)		+= -Iinclude/asm-mips/mach-rm
 load-$(CONFIG_SNI_RM)		+= 0xffffffff80600000
+all-$(CONFIG_SNI_RM)		:= vmlinux.ecoff
 
 #
 # Toshiba JMR-TX3927 board
@@ -647,33 +632,7 @@ vmlinux.64: vmlinux
 
 makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
 
-ifdef CONFIG_BOOT_ELF32
-all:	$(vmlinux-32)
-endif
-
-ifdef CONFIG_BOOT_ELF64
-all:	$(vmlinux-64)
-endif
-
-ifdef CONFIG_MIPS_ATLAS
-all:	vmlinux.srec
-endif
-
-ifdef CONFIG_MIPS_MALTA
-all:	vmlinux.srec
-endif
-
-ifdef CONFIG_MIPS_SEAD
-all:	vmlinux.srec
-endif
-
-ifdef CONFIG_QEMU
-all:	vmlinux.bin
-endif
-
-ifdef CONFIG_SNI_RM
-all:	vmlinux.ecoff
-endif
+all:	$(all-y)
 
 vmlinux.bin: $(vmlinux-32)
 	+@$(call makeboot,$@)
@@ -700,6 +659,14 @@ endif
 archclean:
 	@$(MAKE) $(clean)=arch/mips/boot
 
+define archhelp
+	echo '  vmlinux.ecoff        - ECOFF boot image'
+	echo '  vmlinux.bin          - Raw binary boot image'
+	echo '  vmlinux.srec         - SREC boot image'
+	echo
+	echo '  These will be default as apropriate for a configured platform.'
+endef
+
 CLEAN_FILES += vmlinux.32 \
 	       vmlinux.64 \
 	       vmlinux.ecoff

arch/mips/arc/file.c

@@ -13,63 +13,63 @@
 #include <asm/arc/types.h>
 #include <asm/sgialib.h>
 
-LONG __init
+LONG
 ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer,
                      ULONG N, ULONG *Count)
 {
 	return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count);
 }
 
-LONG __init
+LONG
 ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID)
 {
 	return ARC_CALL3(open, Path, OpenMode, FileID);
 }
 
-LONG __init
+LONG
 ArcClose(ULONG FileID)
 {
 	return ARC_CALL1(close, FileID);
 }
 
-LONG __init
+LONG
 ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count)
 {
 	return ARC_CALL4(read, FileID, Buffer, N, Count);
 }
 
-LONG __init
+LONG
 ArcGetReadStatus(ULONG FileID)
 {
 	return ARC_CALL1(get_rstatus, FileID);
 }
 
-LONG __init
+LONG
 ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count)
 {
 	return ARC_CALL4(write, FileID, Buffer, N, Count);
 }
 
-LONG __init
+LONG
 ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode)
 {
 	return ARC_CALL3(seek, FileID, Position, SeekMode);
 }
 
-LONG __init
+LONG
 ArcMount(char *name, enum linux_mountops op)
 {
 	return ARC_CALL2(mount, name, op);
 }
 
-LONG __init
+LONG
 ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information)
 {
 	return ARC_CALL2(get_finfo, FileID, Information);
 }
 
-LONG __init ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags,
-                                  ULONG AttributeMask)
+LONG ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags,
+                           ULONG AttributeMask)
 {
 	return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask);
 }

arch/mips/au1000/common/Makefile

@@ -12,3 +12,5 @@ obj-y += prom.o irq.o puts.o time.o reset.o \
 
 obj-$(CONFIG_KGDB)		+= dbg_io.o
 obj-$(CONFIG_PCI)		+= pci.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/boot/Makefile

@@ -42,10 +42,6 @@ vmlinux.srec: $(VMLINUX)
 $(obj)/addinitrd: $(obj)/addinitrd.c
 	$(HOSTCC) -o $@ $^
 
-archhelp:
-	@echo	'* vmlinux.ecoff	- ECOFF boot image'
-	@echo	'* vmlinux.srec		- SREC boot image'
-
 clean-files += addinitrd \
 	       elf2ecoff \
 	       vmlinux.bin \

arch/mips/cobalt/Makefile

@@ -7,3 +7,5 @@ obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o
 obj-$(CONFIG_PCI)		+= pci.o
 obj-$(CONFIG_EARLY_PRINTK)	+= console.o
 obj-$(CONFIG_MTD_PHYSMAP)	+= mtd.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/cobalt/serial.c

@@ -55,9 +55,9 @@ static __init int cobalt_uart_add(void)
 	int retval;
 
 	/*
-	 * Cobalt Qube1 and RAQ1 have no UART.
+	 * Cobalt Qube1 has no UART.
 	 */
-	if (cobalt_board_id <= COBALT_BRD_ID_RAQ1)
+	if (cobalt_board_id == COBALT_BRD_ID_QUBE1)
 		return 0;
 
 	pdev = platform_device_alloc("serial8250", -1);

arch/mips/configs/atlas_defconfig

@@ -32,12 +32,9 @@ CONFIG_MIPS_ATLAS=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/bigsur_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/capcella_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 CONFIG_MACH_VR41XX=y
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/cobalt_defconfig

@@ -18,10 +18,8 @@ CONFIG_MIPS_COBALT=y
 # CONFIG_MIPS_SEAD is not set
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_OCELOT is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/db1000_defconfig

@@ -33,12 +33,9 @@ CONFIG_MIPS_DB1000=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/db1100_defconfig

@@ -33,12 +33,9 @@ CONFIG_MIPS_DB1100=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/db1200_defconfig

@@ -33,12 +33,9 @@ CONFIG_MIPS_DB1200=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/db1500_defconfig

@@ -33,12 +33,9 @@ CONFIG_MIPS_DB1500=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/db1550_defconfig

@@ -33,12 +33,9 @@ CONFIG_MIPS_DB1550=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/ddb5477_defconfig

@@ -1,990 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:28 2007
-#
-CONFIG_MIPS=y
-
-#
-# Machine selection
-#
-CONFIG_ZONE_DMA=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
-# CONFIG_MIPS_COBALT is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_WR_PPMC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
-# CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-CONFIG_DDB5477=y
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_QEMU is not set
-# CONFIG_MARKEINS is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_PTSWARM is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_DDB5477_BUS_FREQUENCY=0
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_I8259=y
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_IRQ_CPU=y
-CONFIG_DDB5XXX_COMMON=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-
-#
-# CPU selection
-#
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_VR41XX is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_R5000 is not set
-CONFIG_CPU_R5432=y
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_SYS_HAS_CPU_R5432=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-
-#
-# Kernel type
-#
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-# CONFIG_PAGE_SIZE_64KB is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-# CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_128 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
-# CONFIG_HZ_1024 is not set
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-# CONFIG_KEXEC is not set
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-#
-CONFIG_HW_HAS_PCI=y
-CONFIG_PCI=y
-CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# PCI Hotplug Support
-#
-# CONFIG_HOTPLUG_PCI is not set
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_TRAD_SIGNALS=y
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=y
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_IEEE80211=y
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=y
-CONFIG_IEEE80211_CRYPT_CCMP=y
-CONFIG_IEEE80211_SOFTMAC=y
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=y
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=y
-
-#
-# Misc devices
-#
-CONFIG_SGI_IOC4=y
-# CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_RAID_ATTRS=y
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_DM9000 is not set
-
-#
-# Tulip family network device support
-#
-# CONFIG_NET_TULIP is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-CONFIG_PCNET32=y
-# CONFIG_PCNET32_NAPI is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-# CONFIG_EEPRO100 is not set
-# CONFIG_E100 is not set
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_TLAN is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_VIA_VELOCITY is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-CONFIG_QLA3XXX=y
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3=y
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-CONFIG_NETXEN_NIC=y
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=y
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-# CONFIG_HID is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=y
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=y
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE="ip=any"
-CONFIG_SYS_SUPPORTS_KGDB=y
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_WP512=y
-CONFIG_CRYPTO_TGR192=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=y
-CONFIG_CRYPTO_LRW=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-CONFIG_CRYPTO_SERPENT=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_CAST5=y
-CONFIG_CRYPTO_CAST6=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_KHAZAD=y
-CONFIG_CRYPTO_ANUBIS=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CAMELLIA=y
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC16=y
-CONFIG_CRC32=y
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y

arch/mips/configs/decstation_defconfig

@@ -32,12 +32,9 @@ CONFIG_MACH_DECSTATION=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/e55_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 CONFIG_MACH_VR41XX=y
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/emma2rh_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/excite_defconfig

@@ -33,12 +33,9 @@ CONFIG_BASLER_EXCITE=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/fulong_defconfig

@@ -19,10 +19,8 @@ CONFIG_LEMOTE_FULONG=y
 # CONFIG_MIPS_SEAD is not set
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_OCELOT is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/ip22_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/ip27_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/ip32_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/jazz_defconfig

@@ -32,12 +32,9 @@ CONFIG_MACH_JAZZ=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/jmr3927_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/malta_defconfig

@@ -32,12 +32,9 @@ CONFIG_MIPS_MALTA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/mipssim_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 CONFIG_MIPS_SIM=y
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/mpc30x_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 CONFIG_MACH_VR41XX=y
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/msp71xx_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 CONFIG_PMC_MSP=y
 # CONFIG_PMC_YOSEMITE is not set

arch/mips/configs/ocelot_defconfig

@@ -1,919 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:36 2007
-#
-CONFIG_MIPS=y
-
-#
-# Machine selection
-#
-CONFIG_ZONE_DMA=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
-# CONFIG_MIPS_COBALT is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_WR_PPMC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-CONFIG_MOMENCO_OCELOT=y
-# CONFIG_MOMENCO_OCELOT_G is not set
-# CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_QEMU is not set
-# CONFIG_MARKEINS is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_PTSWARM is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_CPU_RM7K=y
-CONFIG_MIPS_GT64120=y
-CONFIG_SWAP_IO_SPACE=y
-# CONFIG_SYSCLK_75 is not set
-# CONFIG_SYSCLK_83 is not set
-CONFIG_SYSCLK_100=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-
-#
-# CPU selection
-#
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_VR41XX is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_R10000 is not set
-CONFIG_CPU_RM7000=y
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_SYS_HAS_CPU_RM7000=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-
-#
-# Kernel type
-#
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-# CONFIG_PAGE_SIZE_64KB is not set
-CONFIG_BOARD_SCACHE=y
-CONFIG_RM7000_CPU_SCACHE=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-# CONFIG_64BIT_PHYS_ADDR is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-# CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_128 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
-# CONFIG_HZ_1024 is not set
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-# CONFIG_KEXEC is not set
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-# CONFIG_MODULES is not set
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-#
-CONFIG_HW_HAS_PCI=y
-# CONFIG_PCI is not set
-CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-
-#
-# PCI Hotplug Support
-#
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_TRAD_SIGNALS=y
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-# CONFIG_PACKET is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=y
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_IEEE80211=y
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=y
-CONFIG_IEEE80211_CRYPT_CCMP=y
-CONFIG_IEEE80211_SOFTMAC=y
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=y
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=y
-
-#
-# Misc devices
-#
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_RAID_ATTRS=y
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
-# CONFIG_DM9000 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=y
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-# CONFIG_HID is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-CONFIG_FUSE_FS=y
-CONFIG_GENERIC_ACL=y
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=y
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
-CONFIG_SYS_SUPPORTS_KGDB=y
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_WP512=y
-CONFIG_CRYPTO_TGR192=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=y
-CONFIG_CRYPTO_LRW=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=y
-CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_TWOFISH=y
-CONFIG_CRYPTO_TWOFISH_COMMON=y
-CONFIG_CRYPTO_SERPENT=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_CAST5=y
-CONFIG_CRYPTO_CAST6=y
-CONFIG_CRYPTO_TEA=y
-CONFIG_CRYPTO_ARC4=y
-CONFIG_CRYPTO_KHAZAD=y
-CONFIG_CRYPTO_ANUBIS=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CAMELLIA=y
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC16=y
-CONFIG_CRC32=y
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y

arch/mips/configs/pb1100_defconfig

@@ -33,12 +33,9 @@ CONFIG_MIPS_PB1100=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/pb1500_defconfig

@@ -33,12 +33,9 @@ CONFIG_MIPS_PB1500=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/pb1550_defconfig

@@ -33,12 +33,9 @@ CONFIG_MIPS_PB1550=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/pnx8550-jbs_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_PNX8550_JBS=y
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/pnx8550-stb810_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 CONFIG_PNX8550_STB810=y
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/qemu_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 CONFIG_QEMU=y

arch/mips/configs/rbhma4200_defconfig

@@ -30,11 +30,9 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_SEAD is not set
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_OCELOT is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/rbhma4500_defconfig

@@ -20,10 +20,8 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MIPS_SEAD is not set
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_OCELOT is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set

arch/mips/configs/rm200_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/sb1250-swarm_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/sead_defconfig

@@ -32,12 +32,9 @@ CONFIG_MIPS_SEAD=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/tb0219_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 CONFIG_MACH_VR41XX=y
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/tb0226_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 CONFIG_MACH_VR41XX=y
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/tb0287_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 CONFIG_MACH_VR41XX=y
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/workpad_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 CONFIG_MACH_VR41XX=y
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/wrppmc_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 CONFIG_WR_PPMC=y
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/configs/yosemite_defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 CONFIG_PMC_YOSEMITE=y
 # CONFIG_QEMU is not set

arch/mips/ddb5xxx/Kconfig

@@ -1,4 +0,0 @@
-config DDB5477_BUS_FREQUENCY
-	int "bus frequency (in kHZ, 0 for auto-detect)"
-	depends on DDB5477
-	default 0

arch/mips/ddb5xxx/common/Makefile

@@ -1,5 +0,0 @@
-#
-# Makefile for the common code of NEC DDB-Vrc5xxx board
-#
-
-obj-y	 += nile4.o prom.o rtc_ds1386.o

arch/mips/ddb5xxx/common/nile4.c

@@ -1,130 +0,0 @@
-/*
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/common/nile4.c
- *     misc low-level routines for vrc-5xxx controllers.
- *
- * derived from original code by Geert Uytterhoeven <geert@sonycom.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-u32
-ddb_calc_pdar(u32 phys, u32 size, int width,
-	      int on_memory_bus, int pci_visible)
-{
-        u32 maskbits;
-        u32 widthbits;
-
-        switch (size) {
-#if 0                           /* We don't support 4 GB yet */
-        case 0x100000000:       /* 4 GB */
-                maskbits = 4;
-                break;
-#endif
-        case 0x80000000:        /* 2 GB */
-                maskbits = 5;
-                break;
-        case 0x40000000:        /* 1 GB */
-                maskbits = 6;
-                break;
-        case 0x20000000:        /* 512 MB */
-                maskbits = 7;
-                break;
-        case 0x10000000:        /* 256 MB */
-                maskbits = 8;
-                break;
-        case 0x08000000:        /* 128 MB */
-                maskbits = 9;
-                break;
-        case 0x04000000:        /* 64 MB */
-                maskbits = 10;
-                break;
-        case 0x02000000:        /* 32 MB */
-                maskbits = 11;
-                break;
-        case 0x01000000:        /* 16 MB */
-                maskbits = 12;
-                break;
-        case 0x00800000:        /* 8 MB */
-                maskbits = 13;
-                break;
-        case 0x00400000:        /* 4 MB */
-                maskbits = 14;
-                break;
-        case 0x00200000:        /* 2 MB */
-                maskbits = 15;
-                break;
-        case 0:         /* OFF */
-                maskbits = 0;
-                break;
-        default:
-                panic("nile4_set_pdar: unsupported size %p", (void *) size);
-        }
-        switch (width) {
-        case 8:
-                widthbits = 0;
-                break;
-        case 16:
-                widthbits = 1;
-                break;
-        case 32:
-                widthbits = 2;
-                break;
-        case 64:
-                widthbits = 3;
-                break;
-        default:
-                panic("nile4_set_pdar: unsupported width %d", width);
-        }
-
-	return maskbits | (on_memory_bus ? 0x10 : 0) |
-		(pci_visible ? 0x20 : 0) | (widthbits << 6) |
-		(phys & 0xffe00000);
-}
-
-void
-ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
-	     int on_memory_bus, int pci_visible)
-{
-	u32 temp= ddb_calc_pdar(phys, size, width, on_memory_bus, pci_visible);
-	ddb_out32(pdar, temp);
-	ddb_out32(pdar + 4, 0);
-
-        /*
-         * When programming a PDAR, the register should be read immediately
-         * after writing it. This ensures that address decoders are properly
-         * configured.
-	 * [jsun] is this really necessary?
-         */
-        ddb_in32(pdar);
-        ddb_in32(pdar + 4);
-}
-
-/*
- * routines that mess with PCIINITx registers
- */
-
-void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options)
-{
-        switch (type) {
-        case DDB_PCICMD_IACK: /* PCI Interrupt Acknowledge */
-        case DDB_PCICMD_IO:   /* PCI I/O Space */
-        case DDB_PCICMD_MEM:  /* PCI Memory Space */
-        case DDB_PCICMD_CFG:  /* PCI Configuration Space */
-                break;
-        default:
-                panic("nile4_set_pmr: invalid type %d", type);
-        }
-        ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options );
-        ddb_out32(pmr + 4, 0);
-}

arch/mips/ddb5xxx/common/prom.c

@@ -1,132 +0,0 @@
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-#include <asm/ddb5xxx/ddb5xxx.h>
-#include <asm/debug.h>
-
-const char *get_system_type(void)
-{
-	switch (mips_machtype) {
-	case MACH_NEC_DDB5477:		return "NEC DDB Vrc-5477";
-	case MACH_NEC_ROCKHOPPER:	return "NEC Rockhopper";
-	case MACH_NEC_ROCKHOPPERII:     return "NEC RockhopperII";
-	default:			return "Unknown NEC board";
-	}
-}
-
-#if defined(CONFIG_DDB5477)
-void ddb5477_runtime_detection(void);
-#endif
-
-/* [jsun@junsun.net] PMON passes arguments in C main() style */
-void __init prom_init(void)
-{
-	int argc = fw_arg0;
-	char **arg = (char**) fw_arg1;
-	int i;
-
-	/* if user passes kernel args, ignore the default one */
-	if (argc > 1)
-		arcs_cmdline[0] = '\0';
-
-	/* arg[0] is "g", the rest is boot parameters */
-	for (i = 1; i < argc; i++) {
-		if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
-		    >= sizeof(arcs_cmdline))
-			break;
-		strcat(arcs_cmdline, arg[i]);
-		strcat(arcs_cmdline, " ");
-	}
-
-	mips_machgroup = MACH_GROUP_NEC_DDB;
-
-#if defined(CONFIG_DDB5477)
-	ddb5477_runtime_detection();
-	add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
-#endif
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
-
-#if defined(CONFIG_DDB5477)
-
-#define DEFAULT_LCS1_BASE 0x19000000
-#define TESTVAL1 'K'
-#define TESTVAL2 'S'
-
-int board_ram_size;
-void ddb5477_runtime_detection(void)
-{
-	volatile char *test_offset;
-	char saved_test_byte;
-
-        /* Determine if this is a DDB5477 board, or a BSB-VR0300
-           base board.  We can tell by checking for the location of
-           the NVRAM.  It lives at the beginning of LCS1 on the DDB5477,
-           and the beginning of LCS1 on the BSB-VR0300 is flash memory.
-           The first 2K of the NVRAM are reserved, so don't we'll poke
-           around just after that.
-         */
-
-	/* We can only use the PCI bus to distinquish between
-	   the Rockhopper and RockhopperII backplanes and this must
-	   wait until ddb5477_board_init() in setup.c after the 5477
-	   is initialized.  So, until then handle
-	   both Rockhopper and RockhopperII backplanes as Rockhopper 1
-	 */
-
-        test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800);
-        saved_test_byte = *test_offset;
-
-        *test_offset = TESTVAL1;
-        if (*test_offset != TESTVAL1) {
-                /* We couldn't set our test value, so it must not be NVRAM,
-                   so it's a BSB_VR0300 */
-		mips_machtype = MACH_NEC_ROCKHOPPER;
-        } else {
-                /* We may have gotten lucky, and the TESTVAL1 was already
-                   stored at the test location, so we must check a second
-                   test value */
-                *test_offset = TESTVAL2;
-                if (*test_offset != TESTVAL2) {
-                        /* OK, we couldn't set this value either, so it must
-                           definately be a BSB_VR0300 */
-			mips_machtype = MACH_NEC_ROCKHOPPER;
-                } else {
-                        /* We could change the value twice, so it must be
-                        NVRAM, so it's a DDB_VRC5477 */
-			mips_machtype = MACH_NEC_DDB5477;
-                }
-        }
-        /* Restore the original byte */
-        *test_offset = saved_test_byte;
-
-	/* before we know a better way, we will trust PMON for getting
-	 * RAM size
-	 */
-	board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf));
-
-	db_run(printk("DDB run-time detection : %s, %d MB RAM\n",
-				mips_machtype == MACH_NEC_DDB5477 ?
-				"DDB5477" : "Rockhopper",
-				board_ram_size >> 20));
-
-	/* we can't handle ram size > 128 MB */
-	db_assert(board_ram_size <= (128 << 20));
-}
-#endif

arch/mips/ddb5xxx/common/rtc_ds1386.c

@@ -1,170 +0,0 @@
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/common/rtc_ds1386.c
- *     low-level RTC hookups for s for Dallas 1396 chip.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-
-/*
- * This file exports a function, rtc_ds1386_init(), which expects an
- * uncached base address as the argument.  It will set the two function
- * pointers expected by the MIPS generic timer code.
- */
-
-#include <linux/types.h>
-#include <linux/time.h>
-#include <linux/bcd.h>
-
-#include <asm/time.h>
-#include <asm/addrspace.h>
-
-#include <asm/mc146818rtc.h>
-#include <asm/debug.h>
-
-#define	EPOCH		2000
-
-#define	READ_RTC(x)	*(volatile unsigned char*)(rtc_base+x)
-#define	WRITE_RTC(x, y)	*(volatile unsigned char*)(rtc_base+x) = y
-
-static unsigned long rtc_base;
-
-static unsigned long
-rtc_ds1386_get_time(void)
-{
-	u8 byte;
-	u8 temp;
-	unsigned int year, month, day, hour, minute, second;
-	unsigned long flags;
-
-	spin_lock_irqsave(&rtc_lock, flags);
-	/* let us freeze external registers */
-	byte = READ_RTC(0xB);
-	byte &= 0x3f;
-	WRITE_RTC(0xB, byte);
-
-	/* read time data */
-	year = BCD2BIN(READ_RTC(0xA)) + EPOCH;
-	month = BCD2BIN(READ_RTC(0x9) & 0x1f);
-	day = BCD2BIN(READ_RTC(0x8));
-	minute = BCD2BIN(READ_RTC(0x2));
-	second = BCD2BIN(READ_RTC(0x1));
-
-	/* hour is special - deal with it later */
-	temp = READ_RTC(0x4);
-
-	/* enable time transfer */
-	byte |= 0x80;
-	WRITE_RTC(0xB, byte);
-	spin_unlock_irqrestore(&rtc_lock, flags);
-
-	/* calc hour */
-	if (temp & 0x40) {
-		/* 12 hour format */
-		hour = BCD2BIN(temp & 0x1f);
-		if (temp & 0x20) hour += 12; 		/* PM */
-	} else {
-		/* 24 hour format */
-		hour = BCD2BIN(temp & 0x3f);
-	}
-
-	return mktime(year, month, day, hour, minute, second);
-}
-
-static int
-rtc_ds1386_set_time(unsigned long t)
-{
-	struct rtc_time tm;
-	u8 byte;
-	u8 temp;
-	u8 year, month, day, hour, minute, second;
-	unsigned long flags;
-
-	spin_lock_irqsave(&rtc_lock, flags);
-	/* let us freeze external registers */
-	byte = READ_RTC(0xB);
-	byte &= 0x3f;
-	WRITE_RTC(0xB, byte);
-
-	/* convert */
-	to_tm(t, &tm);
-
-
-	/* check each field one by one */
-	year = BIN2BCD(tm.tm_year - EPOCH);
-	if (year != READ_RTC(0xA)) {
-		WRITE_RTC(0xA, year);
-	}
-
-	temp = READ_RTC(0x9);
-	month = BIN2BCD(tm.tm_mon+1);	/* tm_mon starts from 0 to 11 */
-	if (month != (temp & 0x1f)) {
-		WRITE_RTC( 0x9,
-			   (month & 0x1f) | (temp & ~0x1f) );
-	}
-
-	day = BIN2BCD(tm.tm_mday);
-	if (day != READ_RTC(0x8)) {
-		WRITE_RTC(0x8, day);
-	}
-
-	temp = READ_RTC(0x4);
-	if (temp & 0x40) {
-		/* 12 hour format */
-		hour = 0x40;
-		if (tm.tm_hour > 12) {
-			hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f);
-		} else {
-			hour |= BIN2BCD(tm.tm_hour);
-		}
-	} else {
-		/* 24 hour format */
-		hour = BIN2BCD(tm.tm_hour) & 0x3f;
-	}
-	if (hour != temp) WRITE_RTC(0x4, hour);
-
-	minute = BIN2BCD(tm.tm_min);
-	if (minute != READ_RTC(0x2)) {
-		WRITE_RTC(0x2, minute);
-	}
-
-	second = BIN2BCD(tm.tm_sec);
-	if (second != READ_RTC(0x1)) {
-		WRITE_RTC(0x1, second);
-	}
-	spin_unlock_irqrestore(&rtc_lock, flags);
-
-	return 0;
-}
-
-void
-rtc_ds1386_init(unsigned long base)
-{
-	unsigned char byte;
-
-	/* remember the base */
-	rtc_base = base;
-	db_assert((rtc_base & 0xe0000000) == KSEG1);
-
-	/* turn on RTC if it is not on */
-	byte = READ_RTC(0x9);
-	if (byte & 0x80) {
-		byte &= 0x7f;
-		WRITE_RTC(0x9, byte);
-	}
-
-	/* enable time transfer */
-	byte = READ_RTC(0xB);
-	byte |= 0x80;
-	WRITE_RTC(0xB, byte);
-
-	/* set the function pointers */
-	rtc_mips_get_time = rtc_ds1386_get_time;
-	rtc_mips_set_time = rtc_ds1386_set_time;
-}

arch/mips/ddb5xxx/ddb5477/Makefile

@@ -1,9 +0,0 @@
-#
-# Makefile for NEC DDB-Vrc5477 board
-#
-
-obj-y	 		+= ddb5477-platform.o irq.o irq_5477.o setup.o \
-			   lcd44780.o
-
-obj-$(CONFIG_RUNTIME_DEBUG) 	+= debug.o
-obj-$(CONFIG_KGDB)		+= kgdb_io.o

arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c

@@ -1,49 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/serial_8250.h>
-
-#include <asm/ddb5xxx/ddb5477.h>
-
-#define DDB_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
-
-#define DDB5477_PORT(base, int)						\
-{									\
-	.mapbase	= base,						\
-	.irq		= int,						\
-	.uartclk	= 1843200,					\
-	.iotype		= UPIO_MEM,					\
-	.flags		= DDB_UART_FLAGS,				\
-	.regshift	= 3,						\
-}
-
-static struct plat_serial8250_port uart8250_data[] = {
-	DDB5477_PORT(0xbfa04200, VRC5477_IRQ_UART0),
-	DDB5477_PORT(0xbfa04240, VRC5477_IRQ_UART1),
-	{ },
-};
-
-static struct platform_device uart8250_device = {
-	.name			= "serial8250",
-	.id			= PLAT8250_DEV_PLATFORM,
-	.dev			= {
-		.platform_data	= uart8250_data,
-	},
-};
-
-static int __init uart8250_init(void)
-{
-	return platform_device_register(&uart8250_device);
-}
-
-module_init(uart8250_init);
-
-MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("8250 UART probe driver for the NEC DDB5477");

arch/mips/ddb5xxx/ddb5477/debug.c

@@ -1,160 +0,0 @@
-/***********************************************************************
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/ddb5477/debug.c
- *     vrc5477 specific debug routines.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- ***********************************************************************
- */
-
-#include <linux/kernel.h>
-
-#include <asm/mipsregs.h>
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-typedef struct {
-       const char *regname;
-       unsigned regaddr;
-} Register;
-
-void jsun_show_regs(char *name, Register *regs)
-{
-	int i;
-
-	printk("\nshow regs: %s\n", name);
-	for(i=0;regs[i].regname!= NULL; i++) {
-		printk("%-16s= %08x\t\t(@%08x)\n",
-		       regs[i].regname,
-		       *(unsigned *)(regs[i].regaddr),
-		       regs[i].regaddr);
-	}
-}
-
-static Register int_regs[] = {
-	{"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0},
-	{"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1},
-	{"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2},
-	{"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3},
-	{"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT},
-	{"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT},
-	{"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT},
-	{"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT},
-	{"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT},
-	{"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT},
-	{"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0},
-	{"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1},
-	{NULL, 0x0}
-};
-
-void vrc5477_show_int_regs()
-{
-	jsun_show_regs("interrupt registers", int_regs);
-	printk("CPU CAUSE = %08x\n", read_c0_cause());
-	printk("CPU STATUS = %08x\n", read_c0_status());
-}
-static Register pdar_regs[] = {
-        {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
-        {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
-        {"DDB_LCS0", DDB_BASE + DDB_LCS0},
-        {"DDB_LCS1", DDB_BASE + DDB_LCS1},
-        {"DDB_LCS2", DDB_BASE + DDB_LCS2},
-        {"DDB_INTCS", DDB_BASE + DDB_INTCS},
-        {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
-        {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
-        {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
-        {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
-        {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
-        {NULL, 0x0}
-};
-void vrc5477_show_pdar_regs(void)
-{
-        jsun_show_regs("PDAR regs", pdar_regs);
-}
-
-static Register bar_regs[] = {
-        {"DDB_BARC0", DDB_BASE + DDB_BARC0},
-        {"DDB_BARM010", DDB_BASE + DDB_BARM010},
-        {"DDB_BARM230", DDB_BASE + DDB_BARM230},
-        {"DDB_BAR00", DDB_BASE + DDB_BAR00},
-        {"DDB_BAR10", DDB_BASE + DDB_BAR10},
-        {"DDB_BAR20", DDB_BASE + DDB_BAR20},
-        {"DDB_BAR30", DDB_BASE + DDB_BAR30},
-        {"DDB_BAR40", DDB_BASE + DDB_BAR40},
-        {"DDB_BAR50", DDB_BASE + DDB_BAR50},
-        {"DDB_BARB0", DDB_BASE + DDB_BARB0},
-        {"DDB_BARC1", DDB_BASE + DDB_BARC1},
-        {"DDB_BARM011", DDB_BASE + DDB_BARM011},
-        {"DDB_BARM231", DDB_BASE + DDB_BARM231},
-        {"DDB_BAR01", DDB_BASE + DDB_BAR01},
-        {"DDB_BAR11", DDB_BASE + DDB_BAR11},
-        {"DDB_BAR21", DDB_BASE + DDB_BAR21},
-        {"DDB_BAR31", DDB_BASE + DDB_BAR31},
-        {"DDB_BAR41", DDB_BASE + DDB_BAR41},
-        {"DDB_BAR51", DDB_BASE + DDB_BAR51},
-        {"DDB_BARB1", DDB_BASE + DDB_BARB1},
-        {NULL, 0x0}
-};
-void vrc5477_show_bar_regs(void)
-{
-        jsun_show_regs("BAR regs", bar_regs);
-}
-
-static Register pci_regs[] = {
-        {"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
-        {"DDB_PCIW1", DDB_BASE + DDB_PCIW1},
-        {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00},
-        {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10},
-        {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L},
-        {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H},
-        {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L},
-        {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H},
-        {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0},
-        {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0},
-        {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0},
-        {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1},
-        {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01},
-        {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11},
-        {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L},
-        {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H},
-        {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L},
-        {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H},
-        {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1},
-        {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1},
-        {NULL, 0x0}
-};
-void vrc5477_show_pci_regs(void)
-{
-        jsun_show_regs("PCI regs", pci_regs);
-}
-
-static Register lb_regs[] = {
-        {"DDB_LCNFG", DDB_BASE + DDB_LCNFG},
-        {"DDB_LCST0", DDB_BASE + DDB_LCST0},
-        {"DDB_LCST1", DDB_BASE + DDB_LCST1},
-        {"DDB_LCST2", DDB_BASE + DDB_LCST2},
-        {"DDB_ERRADR", DDB_BASE + DDB_ERRADR},
-        {"DDB_ERRCS", DDB_BASE + DDB_ERRCS},
-        {"DDB_BTM", DDB_BASE + DDB_BTM},
-        {"DDB_BCST", DDB_BASE + DDB_BCST},
-        {NULL, 0x0}
-};
-void vrc5477_show_lb_regs(void)
-{
-        jsun_show_regs("Local Bus regs", lb_regs);
-}
-
-void vrc5477_show_all_regs(void)
-{
-	vrc5477_show_pdar_regs();
-	vrc5477_show_pci_regs();
-	vrc5477_show_bar_regs();
-	vrc5477_show_int_regs();
-	vrc5477_show_lb_regs();
-}

arch/mips/ddb5xxx/ddb5477/irq.c

@@ -1,209 +0,0 @@
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- *  arch/mips/ddb5xxx/ddb5477/irq.c
- *     The irq setup and misc routines for DDB5476.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-
-#include <asm/i8259.h>
-#include <asm/irq_cpu.h>
-#include <asm/system.h>
-#include <asm/mipsregs.h>
-#include <asm/debug.h>
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-
-/*
- * IRQ mapping
- *
- *  0-7: 8 CPU interrupts
- *	0 -	software interrupt 0
- *	1 - 	software interrupt 1
- *	2 - 	most Vrc5477 interrupts are routed to this pin
- *	3 - 	(optional) some other interrupts routed to this pin for debugg
- *	4 - 	not used
- *	5 - 	not used
- *	6 - 	not used
- *	7 - 	cpu timer (used by default)
- *
- *  8-39: 32 Vrc5477 interrupt sources
- *	(refer to the Vrc5477 manual)
- */
-
-#define	PCI0			DDB_INTPPES0
-#define	PCI1			DDB_INTPPES1
-
-#define	ACTIVE_LOW		1
-#define	ACTIVE_HIGH		0
-
-#define	LEVEL_SENSE		2
-#define	EDGE_TRIGGER		0
-
-#define	INTA			0
-#define	INTB			1
-#define	INTC			2
-#define	INTD			3
-#define	INTE			4
-
-static inline void
-set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
-{
-	u32 reg_value;
-	u32 reg_bitmask;
-
-	reg_value = ddb_in32(pci);
-	reg_bitmask = 0x3 << (intn * 2);
-
-	reg_value &= ~reg_bitmask;
-	reg_value |= (active | trigger) << (intn * 2);
-	ddb_out32(pci, reg_value);
-}
-
-extern void vrc5477_irq_init(u32 base);
-static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
-
-void __init arch_init_irq(void)
-{
-	/* by default, we disable all interrupts and route all vrc5477
-	 * interrupts to pin 0 (irq 2) */
-	ddb_out32(DDB_INTCTRL0, 0);
-	ddb_out32(DDB_INTCTRL1, 0);
-	ddb_out32(DDB_INTCTRL2, 0);
-	ddb_out32(DDB_INTCTRL3, 0);
-
-	clear_c0_status(0xff00);
-	set_c0_status(0x0400);
-
-	/* setup PCI interrupt attributes */
-	set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
-	set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
-	if (mips_machtype == MACH_NEC_ROCKHOPPERII)
-		set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
-	else
-		set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
-	set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
-	set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
-
-	set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
-	set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
-	set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
-	set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
-	set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
-
-	/*
-	 * for debugging purpose, we enable several error interrupts
-	 * and route them to pin 1. (IP3)
-	 */
-	/* cpu parity check - 0 */
-	ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
-	/* cpu no-target decode - 1 */
-	ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
-	/* local bus read time-out - 7 */
-	ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
-	/* PCI SERR# - 14 */
-	ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
-	/* PCI internal error - 15 */
-	ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
-	/* IOPCI SERR# - 30 */
-	ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
-	/* IOPCI internal error - 31 */
-	ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
-
-	/* init all controllers */
-	init_i8259_irqs();
-	mips_cpu_irq_init();
-	vrc5477_irq_init(VRC5477_IRQ_BASE);
-
-
-	/* setup cascade interrupts */
-	setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
-	setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
-}
-
-u8 i8259_interrupt_ack(void)
-{
-	u8 irq;
-	u32 reg;
-
-	/* Set window 0 for interrupt acknowledge */
-	reg = ddb_in32(DDB_PCIINIT10);
-
-	ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
-	irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
-	ddb_out32(DDB_PCIINIT10, reg);
-
-	return irq;
-}
-/*
- * the first level int-handler will jump here if it is a vrc5477 irq
- */
-#define	NUM_5477_IRQS	32
-static void vrc5477_irq_dispatch(void)
-{
-	u32 intStatus;
-	u32 bitmask;
-	u32 i;
-
-	db_assert(ddb_in32(DDB_INT2STAT) == 0);
-	db_assert(ddb_in32(DDB_INT3STAT) == 0);
-	db_assert(ddb_in32(DDB_INT4STAT) == 0);
-	db_assert(ddb_in32(DDB_NMISTAT) == 0);
-
-	if (ddb_in32(DDB_INT1STAT) != 0) {
-#if defined(CONFIG_RUNTIME_DEBUG)
-		vrc5477_show_int_regs();
-#endif
-		panic("error interrupt has happened.");
-	}
-
-	intStatus = ddb_in32(DDB_INT0STAT);
-
-	if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
-		/* check for i8259 interrupts */
-		if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
-			int i8259_irq = i8259_interrupt_ack();
-			do_IRQ(i8259_irq);
-			return;
-		}
-	}
-
-	for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
-		/* do we need to "and" with the int mask? */
-		if (intStatus & bitmask) {
-			do_IRQ(VRC5477_IRQ_BASE + i);
-			return;
-		}
-	}
-}
-
-#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
-
-asmlinkage void plat_irq_dispatch(void)
-{
-	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
-
-	if (pending & STATUSF_IP7)
-		do_IRQ(CPU_IRQ_BASE + 7);
-	else if (pending & VR5477INTS)
-		vrc5477_irq_dispatch();
-	else if (pending & STATUSF_IP0)
-		do_IRQ(CPU_IRQ_BASE);
-	else if (pending & STATUSF_IP1)
-		do_IRQ(CPU_IRQ_BASE + 1);
-	else
-		spurious_interrupt();
-}

arch/mips/ddb5xxx/ddb5477/irq_5477.c

@@ -1,154 +0,0 @@
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- *  arch/mips/ddb5xxx/ddb5477/irq_5477.c
- *     This file defines the irq handler for Vrc5477.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-/*
- * Vrc5477 defines 32 IRQs.
- *
- * This file exports one function:
- *	vrc5477_irq_init(u32 irq_base);
- */
-
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-
-#include <asm/debug.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-/* number of total irqs supported by Vrc5477 */
-#define	NUM_5477_IRQ		32
-
-static int vrc5477_irq_base = -1;
-
-
-static void
-vrc5477_irq_enable(unsigned int irq)
-{
-	db_assert(vrc5477_irq_base != -1);
-	db_assert(irq >= vrc5477_irq_base);
-	db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
-
-	ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
-}
-
-static void
-vrc5477_irq_disable(unsigned int irq)
-{
-	db_assert(vrc5477_irq_base != -1);
-	db_assert(irq >= vrc5477_irq_base);
-	db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
-
-	ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
-}
-
-static void
-vrc5477_irq_ack(unsigned int irq)
-{
-	db_assert(vrc5477_irq_base != -1);
-	db_assert(irq >= vrc5477_irq_base);
-	db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
-
-	/* clear the interrupt bit */
-	/* some irqs require the driver to clear the sources */
-	ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base));
-
-	/* disable interrupt - some handler will re-enable the irq
-	 * and if the interrupt is leveled, we will have infinite loop
-	 */
-	ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
-}
-
-static void
-vrc5477_irq_end(unsigned int irq)
-{
-	db_assert(vrc5477_irq_base != -1);
-	db_assert(irq >= vrc5477_irq_base);
-	db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
-
-	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-		ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
-}
-
-struct irq_chip vrc5477_irq_controller = {
-	.name = "vrc5477_irq",
-	.ack = vrc5477_irq_ack,
-	.mask = vrc5477_irq_disable,
-	.mask_ack = vrc5477_irq_ack,
-	.unmask = vrc5477_irq_enable,
-	.end = vrc5477_irq_end
-};
-
-void __init vrc5477_irq_init(u32 irq_base)
-{
-	u32 i;
-
-	for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)
-		set_irq_chip(i, &vrc5477_irq_controller);
-
-	vrc5477_irq_base = irq_base;
-}
-
-void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
-{
-	u32 reg_value;
-	u32 reg_bitmask;
-	u32 reg_index;
-
-	db_assert(vrc5477_irq >= 0);
-	db_assert(vrc5477_irq < NUM_5477_IRQ);
-	db_assert(ip >= 0);
-	db_assert((ip < 5) || (ip == 6));
-
-	reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
-	reg_value = ddb_in32(reg_index);
-	reg_bitmask = 7 << (vrc5477_irq % 8 * 4);
-	reg_value &= ~reg_bitmask;
-	reg_value |= ip << (vrc5477_irq % 8 * 4);
-	ddb_out32(reg_index, reg_value);
-}
-
-void ll_vrc5477_irq_enable(int vrc5477_irq)
-{
-	u32 reg_value;
-	u32 reg_bitmask;
-	u32 reg_index;
-
-	db_assert(vrc5477_irq >= 0);
-	db_assert(vrc5477_irq < NUM_5477_IRQ);
-
-	reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
-	reg_value = ddb_in32(reg_index);
-	reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
-	db_assert((reg_value & reg_bitmask) == 0);
-	ddb_out32(reg_index, reg_value | reg_bitmask);
-}
-
-void ll_vrc5477_irq_disable(int vrc5477_irq)
-{
-	u32 reg_value;
-	u32 reg_bitmask;
-	u32 reg_index;
-
-	db_assert(vrc5477_irq >= 0);
-	db_assert(vrc5477_irq < NUM_5477_IRQ);
-
-	reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
-	reg_value = ddb_in32(reg_index);
-	reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
-
-	/* we assert that the interrupt is enabled (perhaps over-zealous) */
-	db_assert( (reg_value & reg_bitmask) != 0);
-	ddb_out32(reg_index, reg_value & ~reg_bitmask);
-}

arch/mips/ddb5xxx/ddb5477/kgdb_io.c

@@ -1,136 +0,0 @@
-/*
- * kgdb io functions for DDB5477.  We use the second serial port (upper one).
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-/* ======================= CONFIG ======================== */
-
-/* [jsun] we use the second serial port for kdb */
-#define         BASE                    0xbfa04240
-#define         MAX_BAUD                115200
-
-/* distance in bytes between two serial registers */
-#define         REG_OFFSET              8
-
-/*
- * 0 - kgdb does serial init
- * 1 - kgdb skip serial init
- */
-static int remoteDebugInitialized = 0;
-
-/*
- * the default baud rate *if* kgdb does serial init
- */
-#define		BAUD_DEFAULT		UART16550_BAUD_38400
-
-/* ======================= END OF CONFIG ======================== */
-
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-#define         UART16550_BAUD_2400             2400
-#define         UART16550_BAUD_4800             4800
-#define         UART16550_BAUD_9600             9600
-#define         UART16550_BAUD_19200            19200
-#define         UART16550_BAUD_38400            38400
-#define         UART16550_BAUD_57600            57600
-#define         UART16550_BAUD_115200           115200
-
-#define         UART16550_PARITY_NONE           0
-#define         UART16550_PARITY_ODD            0x08
-#define         UART16550_PARITY_EVEN           0x18
-#define         UART16550_PARITY_MARK           0x28
-#define         UART16550_PARITY_SPACE          0x38
-
-#define         UART16550_DATA_5BIT             0x0
-#define         UART16550_DATA_6BIT             0x1
-#define         UART16550_DATA_7BIT             0x2
-#define         UART16550_DATA_8BIT             0x3
-
-#define         UART16550_STOP_1BIT             0x0
-#define         UART16550_STOP_2BIT             0x4
-
-/* register offset */
-#define         OFS_RCV_BUFFER          0
-#define         OFS_TRANS_HOLD          0
-#define         OFS_SEND_BUFFER         0
-#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
-#define         OFS_INTR_ID             (2*REG_OFFSET)
-#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
-#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
-#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
-#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
-#define         OFS_LINE_STATUS         (5*REG_OFFSET)
-#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
-#define         OFS_RS232_INPUT         (6*REG_OFFSET)
-#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
-
-#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
-#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
-
-
-/* memory-mapped read/write of the port */
-#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
-#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
-
-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
-{
-        /* disable interrupts */
-        UART16550_WRITE(OFS_INTR_ENABLE, 0);
-
-        /* set up baud rate */
-        {
-                uint32 divisor;
-
-                /* set DIAB bit */
-                UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
-                /* set divisor */
-                divisor = MAX_BAUD / baud;
-                UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
-                UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-
-                /* clear DIAB bit */
-                UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
-        }
-
-        /* set data format */
-        UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
-}
-
-
-uint8 getDebugChar(void)
-{
-        if (!remoteDebugInitialized) {
-                remoteDebugInitialized = 1;
-                debugInit(BAUD_DEFAULT,
-                          UART16550_DATA_8BIT,
-                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-        }
-
-        while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
-        return UART16550_READ(OFS_RCV_BUFFER);
-}
-
-
-int putDebugChar(uint8 byte)
-{
-        if (!remoteDebugInitialized) {
-                remoteDebugInitialized = 1;
-                debugInit(BAUD_DEFAULT,
-                          UART16550_DATA_8BIT,
-                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-        }
-
-        while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
-        UART16550_WRITE(OFS_SEND_BUFFER, byte);
-        return 1;
-}

arch/mips/ddb5xxx/ddb5477/lcd44780.c

@@ -1,96 +0,0 @@
-/*
- * lcd44780.c
- * Simple "driver" for a memory-mapped 44780-style LCD display.
- *
- * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#define LCD44780_COMMAND   ((volatile unsigned char *)0xbe020000)
-#define LCD44780_DATA      ((volatile unsigned char *)0xbe020001)
-
-#define LCD44780_4BIT_1LINE        0x20
-#define LCD44780_4BIT_2LINE        0x28
-#define LCD44780_8BIT_1LINE        0x30
-#define LCD44780_8BIT_2LINE        0x38
-#define LCD44780_MODE_DEC          0x04
-#define LCD44780_MODE_DEC_SHIFT    0x05
-#define LCD44780_MODE_INC          0x06
-#define LCD44780_MODE_INC_SHIFT    0x07
-#define LCD44780_SCROLL_LEFT       0x18
-#define LCD44780_SCROLL_RIGHT      0x1e
-#define LCD44780_CURSOR_UNDERLINE  0x0e
-#define LCD44780_CURSOR_BLOCK      0x0f
-#define LCD44780_CURSOR_OFF        0x0c
-#define LCD44780_CLEAR             0x01
-#define LCD44780_BLANK             0x08
-#define LCD44780_RESTORE           0x0c  // Same as CURSOR_OFF
-#define LCD44780_HOME              0x02
-#define LCD44780_LEFT              0x10
-#define LCD44780_RIGHT             0x14
-
-void lcd44780_wait(void)
-{
-	int i, j;
-	for(i=0; i < 400; i++)
-		for(j=0; j < 10000; j++);
-}
-
-void lcd44780_command(unsigned char c)
-{
-	*LCD44780_COMMAND = c;
-	lcd44780_wait();
-}
-
-void lcd44780_data(unsigned char c)
-{
-	*LCD44780_DATA = c;
-	lcd44780_wait();
-}
-
-void lcd44780_puts(const char* s)
-{
-	int j;
-	int pos = 0;
-
-	lcd44780_command(LCD44780_CLEAR);
-	while(*s) {
-		lcd44780_data(*s);
-		s++;
-		pos++;
-		if (pos == 8) {
-		  /* We must write 32 of spaces to get cursor to 2nd line */
-		  for (j=0; j<32; j++) {
-		    lcd44780_data(' ');
-		  }
-		}
-		if (pos == 16) {
-		  /* We have filled all 16 character positions, so stop
-		     outputing data */
-		  break;
-		}
-	}
-#ifdef LCD44780_PUTS_PAUSE
-	{
-		int i;
-
-		for(i = 1; i < 2000; i++)
-			lcd44780_wait();
-	}
-#endif
-}
-
-void lcd44780_init(void)
-{
-	// The display on the RockHopper is physically a single
-	// 16 char line (two 8 char lines concatenated).  bdl
-	lcd44780_command(LCD44780_8BIT_2LINE);
-	lcd44780_command(LCD44780_MODE_INC);
-	lcd44780_command(LCD44780_CURSOR_BLOCK);
-	lcd44780_command(LCD44780_CLEAR);
-}

arch/mips/ddb5xxx/ddb5477/lcd44780.h

@@ -1,15 +0,0 @@
-/*
- * lcd44780.h
- * Simple "driver" for a memory-mapped 44780-style LCD display.
- *
- * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-void lcd44780_puts(const char* s);
-void lcd44780_init(void);

arch/mips/ddb5xxx/ddb5477/setup.c

@@ -1,399 +0,0 @@
-/*
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- * arch/mips/ddb5xxx/ddb5477/setup.c
- *     Setup file for DDB5477.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/pci.h>
-#include <linux/ide.h>
-#include <linux/irq.h>
-#include <linux/fs.h>
-#include <linux/ioport.h>
-#include <linux/param.h>	/* for HZ */
-#include <linux/major.h>
-#include <linux/kdev_t.h>
-#include <linux/root_dev.h>
-#include <linux/pm.h>
-
-#include <asm/cpu.h>
-#include <asm/bootinfo.h>
-#include <asm/addrspace.h>
-#include <asm/time.h>
-#include <asm/bcache.h>
-#include <asm/irq.h>
-#include <asm/reboot.h>
-#include <asm/gdb-stub.h>
-#include <asm/traps.h>
-#include <asm/debug.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-#include "lcd44780.h"
-
-
-#define	USE_CPU_COUNTER_TIMER	/* whether we use cpu counter */
-
-#define	SP_TIMER_BASE			DDB_SPT1CTRL_L
-#define	SP_TIMER_IRQ			VRC5477_IRQ_SPT1
-
-static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
-
-static void ddb_machine_restart(char *command)
-{
-	static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
-
-	u32 t;
-
-	/* PCI cold reset */
-	ddb_pci_reset_bus();
-
-	/* CPU cold reset */
-	t = ddb_in32(DDB_CPUSTAT);
-	db_assert((t&1));
-	ddb_out32(DDB_CPUSTAT, t);
-
-	/* Call the PROM */
-	back_to_prom();
-}
-
-static void ddb_machine_halt(void)
-{
-	printk("DDB Vrc-5477 halted.\n");
-	while (1);
-}
-
-static void ddb_machine_power_off(void)
-{
-	printk("DDB Vrc-5477 halted. Please turn off the power.\n");
-	while (1);
-}
-
-extern void rtc_ds1386_init(unsigned long base);
-
-static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
-{
-	unsigned int freq;
-	unsigned char c;
-	unsigned int t1, t2;
-	unsigned i;
-
-	ddb_out32(SP_TIMER_BASE, 0xffffffff);
-	ddb_out32(SP_TIMER_BASE+4, 0x1);
-	ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
-
-	/* check if rtc is running */
-	c= *(volatile unsigned char*)rtc_base;
-	for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
-	if (c == *(volatile unsigned char*)rtc_base) {
-		printk("Failed to detect bus frequency.  Use default 83.3MHz.\n");
-		return 83333000;
-	}
-
-	c= *(volatile unsigned char*)rtc_base;
-	while (c == *(volatile unsigned char*)rtc_base);
-	/* we are now at the turn of 1/100th second, if no error. */
-	t1 = ddb_in32(SP_TIMER_BASE+8);
-
-	for (i=0; i< 10; i++) {
-		c= *(volatile unsigned char*)rtc_base;
-		while (c == *(volatile unsigned char*)rtc_base);
-		/* we are now at the turn of another 1/100th second */
-		t2 = ddb_in32(SP_TIMER_BASE+8);
-	}
-
-	ddb_out32(SP_TIMER_BASE+4, 0x0);	/* disable it again */
-
-	freq = (t1 - t2)*10;
-	printk("DDB bus frequency detection : %u \n", freq);
-	return freq;
-}
-
-static void __init ddb_time_init(void)
-{
-	unsigned long rtc_base;
-	unsigned int i;
-
-	/* we have ds1396 RTC chip */
-	if (mips_machtype == MACH_NEC_ROCKHOPPER
-		||  mips_machtype == MACH_NEC_ROCKHOPPERII) {
-		rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
-	} else {
-		rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
-	}
-	rtc_ds1386_init(rtc_base);
-
-	/* do we need to do run-time detection of bus speed? */
-	if (bus_frequency == 0) {
-		bus_frequency = detect_bus_frequency(rtc_base);
-	}
-
-	/* mips_hpt_frequency is 1/2 of the cpu core freq */
-	i =  (read_c0_config() >> 28 ) & 7;
-	if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
-		i = 4;
-	mips_hpt_frequency = bus_frequency*(i+4)/4;
-}
-
-void __init plat_timer_setup(struct irqaction *irq)
-{
-#if defined(USE_CPU_COUNTER_TIMER)
-
-        /* we are using the cpu counter for timer interrupts */
-	setup_irq(CPU_IRQ_BASE + 7, irq);
-
-#else
-
-	/* if we use Special purpose timer 1 */
-	ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
-	ddb_out32(SP_TIMER_BASE+4, 0x1);
-	setup_irq(SP_TIMER_IRQ, irq);
-
-#endif
-}
-
-static void ddb5477_board_init(void);
-
-extern struct pci_controller ddb5477_ext_controller;
-extern struct pci_controller ddb5477_io_controller;
-
-void __init plat_mem_setup(void)
-{
-	/* initialize board - we don't trust the loader */
-        ddb5477_board_init();
-
-	set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
-
-	board_time_init = ddb_time_init;
-
-	_machine_restart = ddb_machine_restart;
-	_machine_halt = ddb_machine_halt;
-	pm_power_off = ddb_machine_power_off;
-
-	/* setup resource limits */
-	ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
-	iomem_resource.end = 0xffffffff;
-
-	/* Reboot on panic */
-	panic_timeout = 180;
-
-	register_pci_controller (&ddb5477_ext_controller);
-	register_pci_controller (&ddb5477_io_controller);
-}
-
-static void __init ddb5477_board_init(void)
-{
-	/* ----------- setup PDARs ------------ */
-
-	/* SDRAM should have been set */
-	db_assert(ddb_in32(DDB_SDRAM0) ==
-		    ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
-
-	/* SDRAM1 should be turned off.  What is this for anyway ? */
-	db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
-
-	/* Setup local bus. */
-
-	/* Flash U12 PDAR and timing. */
-	ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
-	ddb_out32(DDB_LCST0, 0x00090842);
-
-	/* We need to setup LCS1 and LCS2 differently based on the
-	   board_version */
-	if (mips_machtype == MACH_NEC_ROCKHOPPER) {
-		/* Flash U13 PDAR and timing. */
-		ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
-		ddb_out32(DDB_LCST1, 0x00090842);
-
-		/* EPLD (NVRAM, switch, LCD, and mezzanie). */
-		ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
-	} else {
-		/* misc */
-		ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
-		/* mezzanie (?) */
-		ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
-	}
-
-	/* verify VRC5477 base addr */
-	db_assert(ddb_in32(DDB_VRC5477) ==
-		  ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
-
-	/* verify BOOT ROM addr */
-	db_assert(ddb_in32(DDB_BOOTCS) ==
-		  ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
-
-	/* setup PCI windows - window0 for MEM/config, window1 for IO */
-	ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
-	ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
-	ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
-	ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
-
-	/* ------------ reset PCI bus and BARs ----------------- */
-	ddb_pci_reset_bus();
-
-	ddb_out32(DDB_BARM010, 0x00000008);
-	ddb_out32(DDB_BARM011, 0x00000008);
-
-	ddb_out32(DDB_BARC0, 0xffffffff);
-	ddb_out32(DDB_BARM230, 0xffffffff);
-	ddb_out32(DDB_BAR00, 0xffffffff);
-	ddb_out32(DDB_BAR10, 0xffffffff);
-	ddb_out32(DDB_BAR20, 0xffffffff);
-	ddb_out32(DDB_BAR30, 0xffffffff);
-	ddb_out32(DDB_BAR40, 0xffffffff);
-	ddb_out32(DDB_BAR50, 0xffffffff);
-	ddb_out32(DDB_BARB0, 0xffffffff);
-
-	ddb_out32(DDB_BARC1, 0xffffffff);
-	ddb_out32(DDB_BARM231, 0xffffffff);
-	ddb_out32(DDB_BAR01, 0xffffffff);
-	ddb_out32(DDB_BAR11, 0xffffffff);
-	ddb_out32(DDB_BAR21, 0xffffffff);
-	ddb_out32(DDB_BAR31, 0xffffffff);
-	ddb_out32(DDB_BAR41, 0xffffffff);
-	ddb_out32(DDB_BAR51, 0xffffffff);
-	ddb_out32(DDB_BARB1, 0xffffffff);
-
-	/*
-	 * We use pci master register 0  for memory space / config space
-	 * And we use register 1 for IO space.
-	 * Note that for memory space, we bump up the pci base address
-	 * so that we have 1:1 mapping between PCI memory and cpu physical.
-	 * For PCI IO space, it starts from 0 in PCI IO space but with
-	 * DDB_xx_IO_BASE in CPU physical address space.
-	 */
-	ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
-		    DDB_PCI_ACCESS_32);
-	ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
-
-	ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
-		    DDB_PCI_ACCESS_32);
-	ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
-                    DDB_PCI_ACCESS_32);
-
-
-	/* PCI cross window should be set properly */
-	ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
-	ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
-	ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
-	ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
-
-	if (mips_machtype == MACH_NEC_ROCKHOPPER
-	   ||  mips_machtype == MACH_NEC_ROCKHOPPERII) {
-		/* Disable bus diagnostics. */
-		ddb_out32(DDB_PCICTL0_L, 0);
-		ddb_out32(DDB_PCICTL0_H, 0);
-		ddb_out32(DDB_PCICTL1_L, 0);
-		ddb_out32(DDB_PCICTL1_H, 0);
-	}
-
-	if (mips_machtype == MACH_NEC_ROCKHOPPER) {
-		u16			vid;
-		struct pci_bus		bus;
-		struct pci_dev		dev_m1533;
-		extern struct pci_ops 	ddb5477_ext_pci_ops;
-
-		bus.parent      = NULL;    /* we scan the top level only */
-		bus.ops         = &ddb5477_ext_pci_ops;
-		dev_m1533.bus         = &bus;
-		dev_m1533.sysdata     = NULL;
-		dev_m1533.devfn       = 7*8;     // slot 7: M1533 SouthBridge.
-		pci_read_config_word(&dev_m1533, 0, &vid);
-		if (vid == PCI_VENDOR_ID_AL) {
-			printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
-			mips_machtype = MACH_NEC_ROCKHOPPERII;
-		}
-	}
-
-	/* enable USB input buffers */
-	ddb_out32(DDB_PIBMISC, 0x00000007);
-
-	/* For dual-function pins, make them all non-GPIO */
-	ddb_out32(DDB_GIUFUNSEL, 0x0);
-	// ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff);  /* NEC recommanded value */
-
-	if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
-
-		/* enable IDE controller on Ali chip (south bridge) */
-		u8			temp8;
-		struct pci_bus		bus;
-		struct pci_dev		dev_m1533;
-		struct pci_dev		dev_m5229;
-		extern struct pci_ops 	ddb5477_ext_pci_ops;
-
-		/* Setup M1535 registers */
-		bus.parent      = NULL;    /* we scan the top level only */
-		bus.ops         = &ddb5477_ext_pci_ops;
-		dev_m1533.bus         = &bus;
-		dev_m1533.sysdata     = NULL;
-		dev_m1533.devfn       = 7*8;     // slot 7: M1533 SouthBridge.
-
-		/* setup IDE controller
-		 * enable IDE controller (bit 6 - 1)
-		 * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
-		 * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
-		 * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
-		 */
-		pci_write_config_byte(&dev_m1533, 0x58, 0x74);
-
-		/*
-		 * positive decode (bit6 -0)
-		 * enable IDE controler interrupt (bit 4 -1)
-		 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
-		 */
-		pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
-
-		/* Setup M5229 registers */
-		dev_m5229.bus = &bus;
-		dev_m5229.sysdata = NULL;
-		dev_m5229.devfn = 4*8;  	// slot 4 (AD15): M5229 IDE
-
-		/*
-		 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
-		 * M5229 IDSEL is addr:15; see above setting
-		 */
-		pci_read_config_byte(&dev_m5229, 0x50, &temp8);
-		pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
-
-		/*
-		 * enable bus master (bit 2)  and IO decoding  (bit 0)
-		 */
-		pci_read_config_byte(&dev_m5229, 0x04, &temp8);
-		pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
-
-		/*
-		 * enable native, copied from arch/ppc/k2boot/head.S
-		 * TODO - need volatile, need to be portable
-		 */
-		pci_write_config_byte(&dev_m5229, 0x09, 0xef);
-
-		/* Set Primary Channel Command Block Timing */
-		pci_write_config_byte(&dev_m5229, 0x59, 0x31);
-
-		/*
-		 * Enable primary channel 40-pin cable
-		 * M5229 register 0x4a (bit 0)
-		 */
-		pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
-		pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
-	}
-
-	if (mips_machtype == MACH_NEC_ROCKHOPPER
-	   ||  mips_machtype == MACH_NEC_ROCKHOPPERII) {
-		printk("lcd44780: initializing\n");
-		lcd44780_init();
-		lcd44780_puts("MontaVista Linux");
-	}
-}

arch/mips/dec/Makefile

@@ -8,3 +8,5 @@ obj-y		:= ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
 obj-$(CONFIG_PROM_CONSOLE)	+= promcon.o
 obj-$(CONFIG_TC)		+= tc.o
 obj-$(CONFIG_CPU_HAS_WB)	+= wbflush.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/defconfig

@@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y
 # CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_DDB5477 is not set
 # CONFIG_MACH_VR41XX is not set
 # CONFIG_PMC_YOSEMITE is not set
 # CONFIG_QEMU is not set

arch/mips/gt64120/common/Makefile

@@ -1,5 +0,0 @@
-#
-# Makefile for common code of gt64120-based boards.
-#
-
-obj-y	 		+= time.o

arch/mips/gt64120/common/time.c

@@ -1,101 +0,0 @@
-/*
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Galileo Technology chip interrupt handler
- */
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <asm/irq_regs.h>
-#include <asm/gt64120.h>
-
-/*
- * These are interrupt handlers for the GT on-chip interrupts.  They all come
- * in to the MIPS on a single interrupt line, and have to be handled and ack'ed
- * differently than other MIPS interrupts.
- */
-
-static irqreturn_t gt64120_irq(int irq, void *dev_id)
-{
-	unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
-	int handled = 0;
-
-	irq_src = GT_READ(GT_INTRCAUSE_OFS);
-	irq_src_mask = GT_READ(GT_INTRMASK_OFS);
-	int_high_src = GT_READ(GT_HINTRCAUSE_OFS);
-	int_high_src_mask = GT_READ(GT_HINTRMASK_OFS);
-	irq_src = irq_src & irq_src_mask;
-	int_high_src = int_high_src & int_high_src_mask;
-
-	if (irq_src & 0x00000800) {	/* Check for timer interrupt */
-		handled = 1;
-		irq_src &= ~0x00000800;
-		do_timer(1);
-#ifndef CONFIG_SMP
-		update_process_times(user_mode(get_irq_regs()));
-#endif
-	}
-
-	GT_WRITE(GT_INTRCAUSE_OFS, 0);
-	GT_WRITE(GT_HINTRCAUSE_OFS, 0);
-
-	return IRQ_HANDLED;
-}
-
-/*
- * Initializes timer using galileo's built in timer.
- */
-#ifdef CONFIG_SYSCLK_100
-#define Sys_clock (100 * 1000000)	// 100 MHz
-#endif
-#ifdef CONFIG_SYSCLK_83
-#define Sys_clock (83.333 * 1000000)	// 83.333 MHz
-#endif
-#ifdef CONFIG_SYSCLK_75
-#define Sys_clock (75 * 1000000)	// 75 MHz
-#endif
-
-/*
- * This will ignore the standard MIPS timer interrupt handler that is passed in
- * as *irq (=irq0 in ../kernel/time.c).  We will do our own timer interrupt
- * handling.
- */
-void __init plat_timer_setup(struct irqaction *irq)
-{
-	static struct irqaction timer;
-
-	/* Disable timer first */
-	GT_WRITE(GT_TC_CONTROL_OFS, 0);
-	/* Load timer value for 100 Hz */
-	GT_WRITE(GT_TC3_OFS, Sys_clock / HZ);
-
-	/*
-	 * Create the IRQ structure entry for the timer.  Since we're too early
-	 * in the boot process to use the "request_irq()" call, we'll hard-code
-	 * the values to the correct interrupt line.
-	 */
-	timer.handler = gt64120_irq;
-	timer.flags = IRQF_SHARED | IRQF_DISABLED;
-	timer.name = "timer";
-	timer.dev_id = NULL;
-	timer.next = NULL;
-	timer.mask = CPU_MASK_NONE;
-	irq_desc[GT_TIMER].action = &timer;
-
-	enable_irq(GT_TIMER);
-
-	/* Enable timer ints */
-	GT_WRITE(GT_TC_CONTROL_OFS, 0xc0);
-	/* clear Cause register first */
-	GT_WRITE(GT_INTRCAUSE_OFS, 0x0);
-	/* Unmask timer int */
-	GT_WRITE(GT_INTRMASK_OFS, 0x800);
-	/* Clear High int register */
-	GT_WRITE(GT_HINTRCAUSE_OFS, 0x0);
-	/* Mask All interrupts at High cause interrupt */
-	GT_WRITE(GT_HINTRMASK_OFS, 0x0);
-}

arch/mips/gt64120/momenco_ocelot/Makefile

@@ -1,7 +0,0 @@
-#
-# Makefile for Momentum's Ocelot board.
-#
-
-obj-y	 		+= irq.o ocelot-platform.o prom.o reset.o setup.o
-
-obj-$(CONFIG_KGDB)	+= dbg_io.o

arch/mips/gt64120/momenco_ocelot/dbg_io.c

@@ -1,121 +0,0 @@
-
-#include <asm/serial.h> /* For the serial port location and base baud */
-
-/* --- CONFIG --- */
-
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-/* --- END OF CONFIG --- */
-
-#define         UART16550_BAUD_2400             2400
-#define         UART16550_BAUD_4800             4800
-#define         UART16550_BAUD_9600             9600
-#define         UART16550_BAUD_19200            19200
-#define         UART16550_BAUD_38400            38400
-#define         UART16550_BAUD_57600            57600
-#define         UART16550_BAUD_115200           115200
-
-#define         UART16550_PARITY_NONE           0
-#define         UART16550_PARITY_ODD            0x08
-#define         UART16550_PARITY_EVEN           0x18
-#define         UART16550_PARITY_MARK           0x28
-#define         UART16550_PARITY_SPACE          0x38
-
-#define         UART16550_DATA_5BIT             0x0
-#define         UART16550_DATA_6BIT             0x1
-#define         UART16550_DATA_7BIT             0x2
-#define         UART16550_DATA_8BIT             0x3
-
-#define         UART16550_STOP_1BIT             0x0
-#define         UART16550_STOP_2BIT             0x4
-
-/* ----------------------------------------------------- */
-
-/* === CONFIG === */
-
-/* [jsun] we use the second serial port for kdb */
-#define         BASE                    OCELOT_SERIAL1_BASE
-#define         MAX_BAUD                OCELOT_BASE_BAUD
-
-/* === END OF CONFIG === */
-
-#define         REG_OFFSET              4
-
-/* register offset */
-#define         OFS_RCV_BUFFER          0
-#define         OFS_TRANS_HOLD          0
-#define         OFS_SEND_BUFFER         0
-#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
-#define         OFS_INTR_ID             (2*REG_OFFSET)
-#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
-#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
-#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
-#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
-#define         OFS_LINE_STATUS         (5*REG_OFFSET)
-#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
-#define         OFS_RS232_INPUT         (6*REG_OFFSET)
-#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
-
-#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
-#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
-
-
-/* memory-mapped read/write of the port */
-#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
-#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
-
-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
-{
-	/* disable interrupts */
-	UART16550_WRITE(OFS_INTR_ENABLE, 0);
-
-	/* set up baud rate */
-	{
-		uint32 divisor;
-
-		/* set DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
-
-		/* set divisor */
-		divisor = MAX_BAUD / baud;
-		UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
-		UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
-
-		/* clear DIAB bit */
-		UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
-	}
-
-	/* set data format */
-	UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
-}
-
-static int remoteDebugInitialized = 0;
-
-uint8 getDebugChar(void)
-{
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_38400,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
-	return UART16550_READ(OFS_RCV_BUFFER);
-}
-
-
-int putDebugChar(uint8 byte)
-{
-	if (!remoteDebugInitialized) {
-		remoteDebugInitialized = 1;
-		debugInit(UART16550_BAUD_38400,
-			  UART16550_DATA_8BIT,
-			  UART16550_PARITY_NONE, UART16550_STOP_1BIT);
-	}
-
-	while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
-	UART16550_WRITE(OFS_SEND_BUFFER, byte);
-	return 1;
-}

arch/mips/gt64120/momenco_ocelot/irq.c

@@ -1,95 +0,0 @@
-/*
- * Copyright (C) 2000 RidgeRun, Inc.
- * Author: RidgeRun, Inc.
- *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
-#include <asm/system.h>
-
-asmlinkage void plat_irq_dispatch(void)
-{
-	unsigned int pending = read_c0_status() & read_c0_cause();
-
-	if (pending & STATUSF_IP2)		/* int0 hardware line */
-		do_IRQ(2);
-	else if (pending & STATUSF_IP3)		/* int1 hardware line */
-		do_IRQ(3);
-	else if (pending & STATUSF_IP4)		/* int2 hardware line */
-		do_IRQ(4);
-	else if (pending & STATUSF_IP5)		/* int3 hardware line */
-		do_IRQ(5);
-	else if (pending & STATUSF_IP6)		/* int4 hardware line */
-		do_IRQ(6);
-	else if (pending & STATUSF_IP7)		/* cpu timer */
-		do_IRQ(7);
-	else {
-		/*
-		 * Now look at the extended interrupts
-		 */
-		pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
-
-		if (pending & STATUSF_IP8)		/* int6 hardware line */
-			do_IRQ(8);
-		else if (pending & STATUSF_IP9)		/* int7 hardware line */
-			do_IRQ(9);
-		else if (pending & STATUSF_IP10)	/* int8 hardware line */
-			do_IRQ(10);
-		else if (pending & STATUSF_IP11)	/* int9 hardware line */
-			do_IRQ(11);
-	}
-}
-
-void __init arch_init_irq(void)
-{
-	/*
-	 * Clear all of the interrupts while we change the able around a bit.
-	 * int-handler is not on bootstrap
-	 */
-	clear_c0_status(ST0_IM);
-	local_irq_disable();
-
-	mips_cpu_irq_init();
-	rm7k_cpu_irq_init();
-}

arch/mips/gt64120/momenco_ocelot/ocelot-platform.c

@@ -1,46 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- *
- * A NS16552 DUART with a 20MHz crystal.
- *
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/serial_8250.h>
-
-#define OCELOT_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
-
-static struct plat_serial8250_port uart8250_data[] = {
-	{
-		.mapbase	= 0xe0001020,
-		.irq		= 4,
-		.uartclk	= 20000000,
-		.iotype		= UPIO_MEM,
-		.flags		= OCELOT_UART_FLAGS,
-		.regshift	= 2,
-	},
-	{ },
-};
-
-static struct platform_device uart8250_device = {
-	.name			= "serial8250",
-	.id			= PLAT8250_DEV_PLATFORM,
-	.dev			= {
-		.platform_data	= uart8250_data,
-	},
-};
-
-static int __init uart8250_init(void)
-{
-	return platform_device_register(&uart8250_device);
-}
-
-module_init(uart8250_init);
-
-MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("8250 UART probe driver for the Momenco Ocelot");

arch/mips/gt64120/momenco_ocelot/ocelot_pld.h

@@ -1,30 +0,0 @@
-/*
- * Ocelot Board Register Definitions
- *
- * (C) 2001 Red Hat, Inc.
- *
- * GPL'd
- */
-#ifndef __MOMENCO_OCELOT_PLD_H__
-#define __MOMENCO_OCELOT_PLD_H__
-
-#define OCELOT_CS0_ADDR (0xe0020000)
-
-#define OCELOT_REG_BOARDREV (0)
-#define OCELOT_REG_PLD1_ID (1)
-#define OCELOT_REG_PLD2_ID (2)
-#define OCELOT_REG_RESET_STATUS (3)
-#define OCELOT_REG_BOARD_STATUS (4)
-#define OCELOT_REG_CPCI_ID (5)
-#define OCELOT_REG_I2C_CTRL (8)
-#define OCELOT_REG_EEPROM_MODE (9)
-#define OCELOT_REG_INTMASK (10)
-#define OCELOT_REG_INTSTATUS (11)
-#define OCELOT_REG_INTSET (12)
-#define OCELOT_REG_INTCLR (13)
-
-#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y)
-#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x)
-
-
-#endif /* __MOMENCO_OCELOT_PLD_H__ */

arch/mips/gt64120/momenco_ocelot/prom.c

@@ -1,71 +0,0 @@
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-#include <asm/pmon.h>
-
-struct callvectors* debug_vectors;
-
-extern unsigned long gt64120_base;
-
-const char *get_system_type(void)
-{
-	return "Momentum Ocelot";
-}
-
-/* [jsun@junsun.net] PMON passes arguments in C main() style */
-void __init prom_init(void)
-{
-	int argc = fw_arg0;
-	char **arg = (char **) fw_arg1;
-	char **env = (char **) fw_arg2;
-	struct callvectors *cv = (struct callvectors *) fw_arg3;
-	int i;
-
-	/* save the PROM vectors for debugging use */
-	debug_vectors = cv;
-
-	/* arg[0] is "g", the rest is boot parameters */
-	arcs_cmdline[0] = '\0';
-	for (i = 1; i < argc; i++) {
-		if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
-		    >= sizeof(arcs_cmdline))
-			break;
-		strcat(arcs_cmdline, arg[i]);
-		strcat(arcs_cmdline, " ");
-	}
-
-	mips_machgroup = MACH_GROUP_MOMENCO;
-	mips_machtype = MACH_MOMENCO_OCELOT;
-
-	while (*env) {
-		if (strncmp("gtbase", *env, 6) == 0) {
-			gt64120_base = simple_strtol(*env + strlen("gtbase="),
-							NULL, 16);
-			break;
-		}
-		*env++;
-	}
-
-	debug_vectors->printf("Booting Linux kernel...\n");
-
-	/* All the boards have at least 64MiB. If there's more, we
-	   detect and register it later */
-	add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
-}
-
-void __init prom_free_prom_memory(void)
-{
-}

arch/mips/gt64120/momenco_ocelot/reset.c

@@ -1,47 +0,0 @@
-/*
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * Copyright (C) 1997, 2001 Ralf Baechle
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <linux/delay.h>
-
-void momenco_ocelot_restart(char *command)
-{
-	void *nvram = ioremap_nocache(0x2c807000, 0x1000);
-
-	if (!nvram) {
-		printk(KERN_NOTICE "ioremap of reset register failed\n");
-		return;
-	}
-	writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
-					assert reset in 1/16 second */
-	mdelay(10+(1000/16));
-	iounmap(nvram);
-	printk(KERN_NOTICE "Watchdog reset failed\n");
-}
-
-void momenco_ocelot_halt(void)
-{
-	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
-	while (1)
-		__asm__(".set\tmips3\n\t"
-	                "wait\n\t"
-			".set\tmips0");
-}
-
-void momenco_ocelot_power_off(void)
-{
-	momenco_ocelot_halt();
-}

arch/mips/gt64120/momenco_ocelot/setup.c

@@ -1,365 +0,0 @@
-/*
- * setup.c
- *
- * BRIEF MODULE DESCRIPTION
- * Momentum Computer Ocelot (CP7000) - board dependent boot routines
- *
- * Copyright (C) 1996, 1997, 2001, 06  Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2000 RidgeRun, Inc.
- * Copyright (C) 2001 Red Hat, Inc.
- * Copyright (C) 2002 Momentum Computer
- *
- * Author: RidgeRun, Inc.
- *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/timex.h>
-#include <linux/vmalloc.h>
-#include <linux/pm.h>
-
-#include <asm/time.h>
-#include <asm/bootinfo.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/pci.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/traps.h>
-#include <linux/bootmem.h>
-#include <linux/initrd.h>
-#include <asm/gt64120.h>
-#include "ocelot_pld.h"
-
-unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
-
-/* These functions are used for rebooting or halting the machine*/
-extern void momenco_ocelot_restart(char *command);
-extern void momenco_ocelot_halt(void);
-extern void momenco_ocelot_power_off(void);
-
-extern void momenco_ocelot_irq_setup(void);
-
-static char reset_reason;
-
-#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
-
-static void __init setup_l3cache(unsigned long size);
-
-/* setup code for a handoff from a version 1 PMON 2000 PROM */
-static void PMON_v1_setup(void)
-{
-	/* A wired TLB entry for the GT64120A and the serial port. The
-	   GT64120A is going to be hit on every IRQ anyway - there's
-	   absolutely no point in letting it be a random TLB entry, as
-	   it'll just cause needless churning of the TLB. And we use
-	   the other half for the serial port, which is just a PITA
-	   otherwise :)
-
-		Device			Physical	Virtual
-		GT64120 Internal Regs	0x24000000	0xe0000000
-		UARTs (CS2)		0x2d000000	0xe0001000
-	*/
-	add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
-
-	/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
-	   in the CS[012] region. We can't use ioremap() yet. The NVRAM
-	   is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
-
-		Ocelot PLD (CS0)	0x2c000000	0xe0020000
-		NVRAM			0x2c800000	0xe0030000
-	*/
-
-	add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
-
-	/* Relocate the CS3/BootCS region */
-  	GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
-
-	/* Relocate CS[012] */
- 	GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
-
-	/* Relocate the GT64120A itself... */
-	GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
-	mb();
-	gt64120_base = 0xe0000000;
-
-	/* ...and the PCI0 view of it. */
-	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
-	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
-	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
-	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
-}
-
-/* setup code for a handoff from a version 2 PMON 2000 PROM */
-void PMON_v2_setup()
-{
-	/* A wired TLB entry for the GT64120A and the serial port. The
-	   GT64120A is going to be hit on every IRQ anyway - there's
-	   absolutely no point in letting it be a random TLB entry, as
-	   it'll just cause needless churning of the TLB. And we use
-	   the other half for the serial port, which is just a PITA
-	   otherwise :)
-
-		Device			Physical	Virtual
-		GT64120 Internal Regs	0xf4000000	0xe0000000
-		UARTs (CS2)		0xfd000000	0xe0001000
-	*/
-	add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
-
-	/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
-	   in the CS[012] region. We can't use ioremap() yet. The NVRAM
-	   is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
-
-		Ocelot PLD (CS0)	0xfc000000	0xe0020000
-		NVRAM			0xfc800000	0xe0030000
-	*/
-	add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
-
-	gt64120_base = 0xe0000000;
-}
-
-void __init plat_mem_setup(void)
-{
-	void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
-	unsigned int tmpword;
-
-	_machine_restart = momenco_ocelot_restart;
-	_machine_halt = momenco_ocelot_halt;
-	pm_power_off = momenco_ocelot_power_off;
-
-	/*
-	 * initrd_start = (unsigned long)ocelot_initrd_start;
-	 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
-	 * initrd_below_start_ok = 1;
-	 */
-
-	/* do handoff reconfiguration */
-	if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
-		PMON_v1_setup();
-	else
-		PMON_v2_setup();
-
-	/* Turn off the Bit-Error LED */
-	OCELOT_PLD_WRITE(0x80, INTCLR);
-
-	/* Relocate all the PCI1 stuff, not that we use it */
-	GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
-	GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
-	GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
-
-	/* Relocate PCI0 I/O and Mem0 */
-	GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
-	GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
-
-	/* Relocate PCI0 Mem1 */
-	GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
-
-	/* For the initial programming, we assume 512MB configuration */
-	/* Relocate the CPU's view of the RAM... */
-	GT_WRITE(GT_SCS10LD_OFS, 0);
-	GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
-	GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
-	GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
-
-	GT_WRITE(GT_SCS1LD_OFS, 0xff);
-	GT_WRITE(GT_SCS1HD_OFS, 0x00);
-	GT_WRITE(GT_SCS0LD_OFS, 0);
-	GT_WRITE(GT_SCS0HD_OFS, 0xff);
-	GT_WRITE(GT_SCS3LD_OFS, 0xff);
-	GT_WRITE(GT_SCS3HD_OFS, 0x00);
-	GT_WRITE(GT_SCS2LD_OFS, 0);
-	GT_WRITE(GT_SCS2HD_OFS, 0xff);
-
-	/* ...and the PCI0 view of it. */
-	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
-	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
-	GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
-	GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
-	GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
-	GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
-
-	tmpword = OCELOT_PLD_READ(BOARDREV);
-	if (tmpword < 26)
-		printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
-	else
-		printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
-
-	tmpword = OCELOT_PLD_READ(PLD1_ID);
-	printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
-	tmpword = OCELOT_PLD_READ(PLD2_ID);
-	printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
-	tmpword = OCELOT_PLD_READ(RESET_STATUS);
-	printk("Reset reason: 0x%x\n", tmpword);
-	reset_reason = tmpword;
-	OCELOT_PLD_WRITE(0xff, RESET_STATUS);
-
-	tmpword = OCELOT_PLD_READ(BOARD_STATUS);
-	printk("Board Status register: 0x%02x\n", tmpword);
-	printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
-	printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
-	printk("  - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
-	printk("  - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
-	printk("  - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
-
-	if (tmpword&12)
-		l3func((1<<(((tmpword&12) >> 2)+20)));
-
-	switch(tmpword &3) {
-	case 3:
-		/* 512MiB */
-		/* Decoders are allready set -- just add the
-		 * appropriate region */
-		add_memory_region( 0x40<<20,  0xC0<<20, BOOT_MEM_RAM);
-		add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
-		break;
-	case 2:
-		/* 256MiB -- two banks of 128MiB */
-		GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
-		GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
-		GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
-
-		GT_WRITE(GT_SCS0HD_OFS, 0x7f);
-		GT_WRITE(GT_SCS2LD_OFS, 0x80);
-		GT_WRITE(GT_SCS2HD_OFS, 0xff);
-
-		/* reconfigure the PCI0 interface view of memory */
-		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
-		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
-		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
-		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
-
-		add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
-		add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
-		break;
-	case 1:
-		/* 128MiB -- 64MiB per bank */
-		GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
-		GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
-		GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
-
-		GT_WRITE(GT_SCS0HD_OFS, 0x3f);
-		GT_WRITE(GT_SCS2LD_OFS, 0x40);
-		GT_WRITE(GT_SCS2HD_OFS, 0x7f);
-
-		/* reconfigure the PCI0 interface view of memory */
-		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
-		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
-		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
-		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
-
-		/* add the appropriate region */
-		add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
-		break;
-	case 0:
-		/* 64MiB */
-		GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
-		GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
-		GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
-
-		GT_WRITE(GT_SCS0HD_OFS, 0x1f);
-		GT_WRITE(GT_SCS2LD_OFS, 0x20);
-		GT_WRITE(GT_SCS2HD_OFS, 0x3f);
-
-		/* reconfigure the PCI0 interface view of memory */
-		GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
-		GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
-		GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
-		GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
-
-		break;
-	}
-
-	/* Fix up the DiskOnChip mapping */
-	GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
-}
-
-extern int rm7k_tcache_enabled;
-/*
- * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
- */
-#define Page_Invalidate_T 0x16
-static void __init setup_l3cache(unsigned long size)
-{
-	int register i;
-	unsigned long tmp;
-
-	printk("Enabling L3 cache...");
-
-	/* Enable the L3 cache in the GT64120A's CPU Configuration register */
-	tmp = GT_READ(GT_CPU_OFS);
-	GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
-
-	/* Enable the L3 cache in the CPU */
-	set_c0_config(1<<12 /* CONF_TE */);
-
-	/* Clear the cache */
-	write_c0_taglo(0);
-	write_c0_taghi(0);
-
-	for (i=0; i < size; i+= 4096) {
-		__asm__ __volatile__ (
-			".set noreorder\n\t"
-			".set mips3\n\t"
-			"cache %1, (%0)\n\t"
-			".set mips0\n\t"
-			".set reorder"
-			:
-			: "r" (KSEG0ADDR(i)),
-			  "i" (Page_Invalidate_T));
-	}
-
-	/* Let the RM7000 MM code know that the tertiary cache is enabled */
-	rm7k_tcache_enabled = 1;
-
-	printk("Done\n");
-}
-
-
-/* This needs to be one of the first initcalls, because no I/O port access
-   can work before this */
-
-static int io_base_ioremap(void)
-{
-	void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
-
-	if (!io_remap_range) {
-		panic("Could not ioremap I/O port range");
-	}
-	set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
-
-	return 0;
-}
-
-module_init(io_base_ioremap);

arch/mips/gt64120/wrppmc/Makefile

@@ -10,3 +10,5 @@
 #
 
 obj-y += irq.o reset.o setup.o time.o pci.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/jazz/Makefile

@@ -3,3 +3,5 @@
 #
 
 obj-y	 	:= irq.o jazzdma.o jazz-platform.o reset.o setup.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/jmr3927/common/Makefile

@@ -3,3 +3,5 @@
 #
 
 obj-y	 += prom.o puts.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/jmr3927/rbhma3100/Makefile

@@ -4,3 +4,5 @@
 
 obj-y	 			+= init.o irq.o setup.o
 obj-$(CONFIG_KGDB)		+= kgdb_io.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/kernel/Makefile

@@ -71,3 +71,5 @@ obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
 CFLAGS_cpu-bugs64.o	= $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
 
 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/kernel/asm-offsets.c

@@ -132,7 +132,6 @@ void output_thread_defines(void)
 	offset("#define THREAD_ECODE   ", struct task_struct, \
 	       thread.error_code);
 	offset("#define THREAD_TRAPNO  ", struct task_struct, thread.trap_no);
-	offset("#define THREAD_MFLAGS  ", struct task_struct, thread.mflags);
 	offset("#define THREAD_TRAMP   ", struct task_struct, \
 	       thread.irix_trampoline);
 	offset("#define THREAD_OLDCTX  ", struct task_struct, \

arch/mips/kernel/head.S

@@ -138,7 +138,6 @@
 	.fill	0x400
 #endif
 
-EXPORT(stext)					# used for profiling
 EXPORT(_stext)
 
 #ifndef CONFIG_BOOT_RAW

arch/mips/kernel/kspd.c

@@ -89,7 +89,7 @@ static int sp_stopping = 0;
 #define MTSP_O_EXCL		0x0800
 #define MTSP_O_BINARY		0x8000
 
-#define SP_VPE 1
+extern int tclimit;
 
 struct apsp_table  {
 	int sp;
@@ -225,8 +225,8 @@ void sp_work_handle_request(void)
 	/* Run the syscall at the priviledge of the user who loaded the
 	   SP program */
 
-	if (vpe_getuid(SP_VPE))
-		sp_setfsuidgid( vpe_getuid(SP_VPE), vpe_getgid(SP_VPE));
+	if (vpe_getuid(tclimit))
+		sp_setfsuidgid(vpe_getuid(tclimit), vpe_getgid(tclimit));
 
 	switch (sc.cmd) {
 	/* needs the flags argument translating from SDE kit to
@@ -245,7 +245,7 @@ void sp_work_handle_request(void)
 
  	case MTSP_SYSCALL_EXIT:
 		list_for_each_entry(n, &kspd_notifylist, list)
- 			n->kspd_sp_exit(SP_VPE);
+			n->kspd_sp_exit(tclimit);
 		sp_stopping = 1;
 
 		printk(KERN_DEBUG "KSPD got exit syscall from SP exitcode %d\n",
@@ -255,7 +255,7 @@ void sp_work_handle_request(void)
  	case MTSP_SYSCALL_OPEN:
  		generic.arg1 = translate_open_flags(generic.arg1);
 
- 		vcwd = vpe_getcwd(SP_VPE);
+		vcwd = vpe_getcwd(tclimit);
 
  		/* change to the cwd of the process that loaded the SP program */
 		old_fs = get_fs();
@@ -283,7 +283,7 @@ void sp_work_handle_request(void)
 		break;
  	} /* switch */
 
-	if (vpe_getuid(SP_VPE))
+	if (vpe_getuid(tclimit))
 		sp_setfsuidgid( 0, 0);
 
 	old_fs = get_fs();
@@ -364,10 +364,9 @@ static void startwork(int vpe)
 		}
 
 		INIT_WORK(&work, sp_work);
-		queue_work(workqueue, &work);
-	} else
-		queue_work(workqueue, &work);
+	}
 
+	queue_work(workqueue, &work);
 }
 
 static void stopwork(int vpe)
@@ -389,7 +388,7 @@ static int kspd_module_init(void)
 
 	notify.start = startwork;
 	notify.stop = stopwork;
-	vpe_notify(SP_VPE, &notify);
+	vpe_notify(tclimit, &notify);
 
 	return 0;
 }

arch/mips/kernel/linux32.c

@@ -566,6 +566,13 @@ asmlinkage long sys32_fadvise64_64(int fd, int __pad,
 			flags);
 }
 
+asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_a2,
+	unsigned offset_a3, unsigned len_a4, unsigned len_a5)
+{
+	return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3),
+	                     merge_64(len_a4, len_a5));
+}
+
 save_static_function(sys32_clone);
 static int noinline __used
 _sys32_clone(nabi_no_regargs struct pt_regs regs)

arch/mips/kernel/machine_kexec.c

@@ -14,7 +14,7 @@
 #include <asm/page.h>
 
 extern const unsigned char relocate_new_kernel[];
-extern const unsigned int relocate_new_kernel_size;
+extern const size_t relocate_new_kernel_size;
 
 extern unsigned long kexec_start_address;
 extern unsigned long kexec_indirection_page;
@@ -40,6 +40,8 @@ machine_crash_shutdown(struct pt_regs *regs)
 {
 }
 
+typedef void (*noretfun_t)(void) __attribute__((noreturn));
+
 void
 machine_kexec(struct kimage *image)
 {
@@ -51,7 +53,8 @@ machine_kexec(struct kimage *image)
 	  (unsigned long)page_address(image->control_code_page);
 
 	kexec_start_address = image->start;
-	kexec_indirection_page = phys_to_virt(image->head & PAGE_MASK);
+	kexec_indirection_page =
+		(unsigned long) phys_to_virt(image->head & PAGE_MASK);
 
 	memcpy((void*)reboot_code_buffer, relocate_new_kernel,
 	       relocate_new_kernel_size);
@@ -67,7 +70,7 @@ machine_kexec(struct kimage *image)
 	       phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
 		if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
 		    *ptr & IND_DESTINATION)
-			*ptr = phys_to_virt(*ptr);
+			*ptr = (unsigned long) phys_to_virt(*ptr);
 	}
 
 	/*
@@ -78,8 +81,8 @@ machine_kexec(struct kimage *image)
 	flush_icache_range(reboot_code_buffer,
 			   reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE);
 
-	printk("Will call new kernel at %08x\n", image->start);
+	printk("Will call new kernel at %08lx\n", image->start);
 	printk("Bye ...\n");
 	flush_cache_all();
-	((void (*)(void))reboot_code_buffer)();
+	((noretfun_t) reboot_code_buffer)();
 }

arch/mips/kernel/mips-mt-fpaff.c

@@ -50,6 +50,7 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
 	cpumask_t effective_mask;
 	int retval;
 	struct task_struct *p;
+	struct thread_info *ti;
 
 	if (len < sizeof(new_mask))
 		return -EINVAL;
@@ -93,16 +94,16 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
 	read_unlock(&tasklist_lock);
 
 	/* Compute new global allowed CPU set if necessary */
-	if ((p->thread.mflags & MF_FPUBOUND)
-	&& cpus_intersects(new_mask, mt_fpu_cpumask)) {
+	ti = task_thread_info(p);
+	if (test_ti_thread_flag(ti, TIF_FPUBOUND) &&
+	    cpus_intersects(new_mask, mt_fpu_cpumask)) {
 		cpus_and(effective_mask, new_mask, mt_fpu_cpumask);
 		retval = set_cpus_allowed(p, effective_mask);
 	} else {
-		p->thread.mflags &= ~MF_FPUBOUND;
+		clear_ti_thread_flag(ti, TIF_FPUBOUND);
 		retval = set_cpus_allowed(p, new_mask);
 	}
 
-
 out_unlock:
 	put_task_struct(p);
 	unlock_cpu_hotplug();

arch/mips/kernel/mips-mt.c

@@ -21,6 +21,28 @@
 #include <asm/r4kcache.h>
 #include <asm/cacheflush.h>
 
+int vpelimit;
+
+static int __init maxvpes(char *str)
+{
+	get_option(&str, &vpelimit);
+
+	return 1;
+}
+
+__setup("maxvpes=", maxvpes);
+
+int tclimit;
+
+static int __init maxtcs(char *str)
+{
+	get_option(&str, &tclimit);
+
+	return 1;
+}
+
+__setup("maxtcs=", maxtcs);
+
 /*
  * Dump new MIPS MT state for the core. Does not leave TCs halted.
  * Takes an argument which taken to be a pre-call MVPControl value.

arch/mips/kernel/process.c

@@ -77,7 +77,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
 	status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK);
 #ifdef CONFIG_64BIT
 	status &= ~ST0_FR;
-	status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR;
+	status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR;
 #endif
 	status |= KU_USER;
 	regs->cp0_status = status;

arch/mips/kernel/ptrace.c

@@ -20,11 +20,11 @@
 #include <linux/mm.h>
 #include <linux/errno.h>
 #include <linux/ptrace.h>
-#include <linux/audit.h>
 #include <linux/smp.h>
 #include <linux/user.h>
 #include <linux/security.h>
-#include <linux/signal.h>
+#include <linux/audit.h>
+#include <linux/seccomp.h>
 
 #include <asm/byteorder.h>
 #include <asm/cpu.h>
@@ -470,12 +470,17 @@ static inline int audit_arch(void)
  */
 asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
 {
+	/* do the secure computing check first */
+	if (!entryexit)
+		secure_computing(regs->regs[0]);
+
 	if (unlikely(current->audit_context) && entryexit)
 		audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]),
 		                   regs->regs[2]);
 
 	if (!(current->ptrace & PT_PTRACED))
 		goto out;
+
 	if (!test_thread_flag(TIF_SYSCALL_TRACE))
 		goto out;
 
@@ -493,9 +498,10 @@ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
 		send_sig(current->exit_code, current, 1);
 		current->exit_code = 0;
 	}
- out:
+
+out:
 	if (unlikely(current->audit_context) && !entryexit)
-		audit_syscall_entry(audit_arch(), regs->regs[2],
+		audit_syscall_entry(audit_arch(), regs->regs[0],
 				    regs->regs[4], regs->regs[5],
 				    regs->regs[6], regs->regs[7]);
 }

arch/mips/kernel/relocate_kernel.S

@@ -14,67 +14,69 @@
 #include <asm/stackframe.h>
 #include <asm/addrspace.h>
 
-	.globl relocate_new_kernel
-relocate_new_kernel:
-
-	PTR_L	s0, kexec_indirection_page
-	PTR_L	s1, kexec_start_address
+LEAF(relocate_new_kernel)
+	PTR_L		s0, kexec_indirection_page
+	PTR_L		s1, kexec_start_address
 
 process_entry:
-	PTR_L	s2, (s0)
-	PTR_ADD	s0, s0, SZREG
+	PTR_L		s2, (s0)
+	PTR_ADD		s0, s0, SZREG
 
 	/* destination page */
-	and	s3, s2, 0x1
-	beq	s3, zero, 1f
-	and	s4, s2, ~0x1	/* store destination addr in s4 */
-	move	a0, s4
-	b	process_entry
+	and		s3, s2, 0x1
+	beq		s3, zero, 1f
+	and		s4, s2, ~0x1	/* store destination addr in s4 */
+	move		a0, s4
+	b		process_entry
 
 1:
 	/* indirection page, update s0  */
-	and	s3, s2, 0x2
-	beq	s3, zero, 1f
-	and	s0, s2, ~0x2
-	b	process_entry
+	and		s3, s2, 0x2
+	beq		s3, zero, 1f
+	and		s0, s2, ~0x2
+	b		process_entry
 
 1:
 	/* done page */
-	and	s3, s2, 0x4
-	beq	s3, zero, 1f
-	b	done
+	and		s3, s2, 0x4
+	beq		s3, zero, 1f
+	b		done
 1:
 	/* source page */
-	and	s3, s2, 0x8
-	beq	s3, zero, process_entry
-	and	s2, s2, ~0x8
-	li	s6, (1 << PAGE_SHIFT) / SZREG
+	and		s3, s2, 0x8
+	beq		s3, zero, process_entry
+	and		s2, s2, ~0x8
+	li		s6, (1 << PAGE_SHIFT) / SZREG
 
 copy_word:
 	/* copy page word by word */
-	REG_L	s5, (s2)
-	REG_S	s5, (s4)
-	INT_ADD	s4, s4, SZREG
-	INT_ADD	s2, s2, SZREG
-	INT_SUB	s6, s6, 1
-	beq	s6, zero, process_entry
-	b	copy_word
-	b	process_entry
+	REG_L		s5, (s2)
+	REG_S		s5, (s4)
+	PTR_ADD		s4, s4, SZREG
+	PTR_ADD		s2, s2, SZREG
+	LONG_SUB	s6, s6, 1
+	beq		s6, zero, process_entry
+	b		copy_word
+	b		process_entry
 
 done:
 	/* jump to kexec_start_address */
-	j	s1
+	j		s1
+	END(relocate_new_kernel)
 
-	.globl kexec_start_address
 kexec_start_address:
-	.long	0x0
+	EXPORT(kexec_start_address)
+	PTR		0x0
+	.size		kexec_start_address, PTRSIZE
 
-	.globl kexec_indirection_page
 kexec_indirection_page:
-	.long	0x0
+	EXPORT(kexec_indirection_page)
+	PTR		0
+	.size		kexec_indirection_page, PTRSIZE
 
 relocate_new_kernel_end:
 
-	.globl relocate_new_kernel_size
 relocate_new_kernel_size:
-	.long relocate_new_kernel_end - relocate_new_kernel
+	EXPORT(relocate_new_kernel_size)
+	PTR		relocate_new_kernel_end - relocate_new_kernel
+	.size		relocate_new_kernel_size, PTRSIZE

arch/mips/kernel/rtlx.c

@@ -40,12 +40,11 @@
 #include <asm/atomic.h>
 #include <asm/cpu.h>
 #include <asm/processor.h>
+#include <asm/mips_mt.h>
 #include <asm/system.h>
 #include <asm/vpe.h>
 #include <asm/rtlx.h>
 
-#define RTLX_TARG_VPE 1
-
 static struct rtlx_info *rtlx;
 static int major;
 static char module_name[] = "rtlx";
@@ -165,10 +164,10 @@ int rtlx_open(int index, int can_sleep)
 	}
 
 	if (rtlx == NULL) {
-		if( (p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) {
+		if( (p = vpe_get_shared(tclimit)) == NULL) {
 			if (can_sleep) {
 				__wait_event_interruptible(channel_wqs[index].lx_queue,
-				                           (p = vpe_get_shared(RTLX_TARG_VPE)),
+				                           (p = vpe_get_shared(tclimit)),
 				                           ret);
 				if (ret)
 					goto out_fail;
@@ -472,11 +471,24 @@ static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;
 static char register_chrdev_failed[] __initdata =
 	KERN_ERR "rtlx_module_init: unable to register device\n";
 
-static int rtlx_module_init(void)
+static int __init rtlx_module_init(void)
 {
 	struct device *dev;
 	int i, err;
 
+	if (!cpu_has_mipsmt) {
+		printk("VPE loader: not a MIPS MT capable processor\n");
+		return -ENODEV;
+	}
+
+	if (tclimit == 0) {
+		printk(KERN_WARNING "No TCs reserved for AP/SP, not "
+		       "initializing RTLX.\nPass maxtcs=<n> argument as kernel "
+		       "argument\n");
+
+		return -ENODEV;
+	}
+
 	major = register_chrdev(0, module_name, &rtlx_fops);
 	if (major < 0) {
 		printk(register_chrdev_failed);
@@ -501,7 +513,7 @@ static int rtlx_module_init(void)
 	/* set up notifiers */
 	notify.start = starting;
 	notify.stop = stopping;
-	vpe_notify(RTLX_TARG_VPE, &notify);
+	vpe_notify(tclimit, &notify);
 
 	if (cpu_has_vint)
 		set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);

arch/mips/kernel/scall32-o32.S

@@ -662,6 +662,7 @@ einval:	li	v0, -EINVAL
 	sys	sys_signalfd		3
 	sys	sys_timerfd		4
 	sys	sys_eventfd		1
+	sys	sys_fallocate		6	/* 4320 */
 	.endm
 
 	/* We pre-compute the number of _instruction_ bytes needed to

arch/mips/kernel/scall64-64.S

@@ -477,4 +477,5 @@ sys_call_table:
 	PTR	sys_signalfd
 	PTR	sys_timerfd
 	PTR	sys_eventfd
+	PTR	sys_fallocate
 	.size	sys_call_table,.-sys_call_table

arch/mips/kernel/scall64-n32.S

@@ -403,4 +403,5 @@ EXPORT(sysn32_call_table)
 	PTR	compat_sys_signalfd		/* 5280 */
 	PTR	compat_sys_timerfd
 	PTR	sys_eventfd
+	PTR	sys_fallocate
 	.size	sysn32_call_table,.-sysn32_call_table

arch/mips/kernel/scall64-o32.S

@@ -525,4 +525,5 @@ sys_call_table:
 	PTR	compat_sys_signalfd
 	PTR	compat_sys_timerfd
 	PTR	sys_eventfd
+	PTR	sys_fallocate			/* 4320 */
 	.size	sys_call_table,.-sys_call_table

arch/mips/kernel/signal32.c

@@ -18,7 +18,6 @@
 #include <linux/errno.h>
 #include <linux/wait.h>
 #include <linux/ptrace.h>
-#include <linux/compat.h>
 #include <linux/suspend.h>
 #include <linux/compiler.h>
 #include <linux/uaccess.h>

arch/mips/kernel/smp.c

@@ -194,6 +194,61 @@ void smp_call_function_interrupt(void)
 	}
 }
 
+int smp_call_function_single(int cpu, void (*func) (void *info), void *info,
+			     int retry, int wait)
+{
+	struct call_data_struct data;
+	int me;
+
+	/*
+	 * Can die spectacularly if this CPU isn't yet marked online
+	 */
+	if (!cpu_online(cpu))
+		return 0;
+
+	me = get_cpu();
+	BUG_ON(!cpu_online(me));
+
+	if (cpu == me) {
+		local_irq_disable();
+		func(info);
+		local_irq_enable();
+		put_cpu();
+		return 0;
+	}
+
+	/* Can deadlock when called with interrupts disabled */
+	WARN_ON(irqs_disabled());
+
+	data.func = func;
+	data.info = info;
+	atomic_set(&data.started, 0);
+	data.wait = wait;
+	if (wait)
+		atomic_set(&data.finished, 0);
+
+	spin_lock(&smp_call_lock);
+	call_data = &data;
+	smp_mb();
+
+	/* Send a message to the other CPU */
+	core_send_ipi(cpu, SMP_CALL_FUNCTION);
+
+	/* Wait for response */
+	/* FIXME: lock-up detection, backtrace on lock-up */
+	while (atomic_read(&data.started) != 1)
+		barrier();
+
+	if (wait)
+		while (atomic_read(&data.finished) != 1)
+			barrier();
+	call_data = NULL;
+	spin_unlock(&smp_call_lock);
+
+	put_cpu();
+	return 0;
+}
+
 static void stop_this_cpu(void *dummy)
 {
 	/*

arch/mips/kernel/smtc.c

@@ -86,25 +86,11 @@ unsigned int smtc_status = 0;
 
 /* Boot command line configuration overrides */
 
-static int vpelimit = 0;
-static int tclimit = 0;
 static int ipibuffers = 0;
 static int nostlb = 0;
 static int asidmask = 0;
 unsigned long smtc_asid_mask = 0xff;
 
-static int __init maxvpes(char *str)
-{
-	get_option(&str, &vpelimit);
-	return 1;
-}
-
-static int __init maxtcs(char *str)
-{
-	get_option(&str, &tclimit);
-	return 1;
-}
-
 static int __init ipibufs(char *str)
 {
 	get_option(&str, &ipibuffers);
@@ -137,8 +123,6 @@ static int __init asidmask_set(char *str)
 	return 1;
 }
 
-__setup("maxvpes=", maxvpes);
-__setup("maxtcs=", maxtcs);
 __setup("ipibufs=", ipibufs);
 __setup("nostlb", stlb_disable);
 __setup("asidmask=", asidmask_set);
@@ -168,9 +152,9 @@ static int __init tintq(char *str)
 
 __setup("tintq=", tintq);
 
-int imstuckcount[2][8];
+static int imstuckcount[2][8];
 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
-int vpemask[2][8] = {
+static int vpemask[2][8] = {
 	{0, 0, 1, 0, 0, 0, 0, 1},
 	{0, 0, 0, 0, 0, 0, 0, 1}
 };
@@ -540,7 +524,7 @@ void mipsmt_prepare_cpus(void)
  * (unsigned long)idle->thread_info the gp
  *
  */
-void smtc_boot_secondary(int cpu, struct task_struct *idle)
+void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
 {
 	extern u32 kernelsp[NR_CPUS];
 	long flags;
@@ -876,7 +860,7 @@ void deferred_smtc_ipi(void)
  * Send clock tick to all TCs except the one executing the funtion
  */
 
-void smtc_timer_broadcast(int vpe)
+void smtc_timer_broadcast(void)
 {
 	int cpu;
 	int myTC = cpu_data[smp_processor_id()].tc_id;
@@ -975,7 +959,12 @@ static void ipi_irq_dispatch(void)
 	do_IRQ(cpu_ipi_irq);
 }
 
-static struct irqaction irq_ipi;
+static struct irqaction irq_ipi = {
+	.handler	= ipi_interrupt,
+	.flags		= IRQF_DISABLED,
+	.name		= "SMTC_IPI",
+	.flags		= IRQF_PERCPU
+};
 
 static void setup_cross_vpe_interrupts(unsigned int nvpe)
 {
@@ -987,13 +976,8 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe)
 
 	set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
 
-	irq_ipi.handler = ipi_interrupt;
-	irq_ipi.flags = IRQF_DISABLED;
-	irq_ipi.name = "SMTC_IPI";
-
 	setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
 
-	irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU;
 	set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
 }
 

arch/mips/kernel/syscall.c

@@ -281,16 +281,24 @@ asmlinkage int sys_set_thread_area(unsigned long addr)
 
 asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
 {
-	int	tmp;
-
-	switch(cmd) {
+	switch (cmd) {
 	case MIPS_ATOMIC_SET:
 		printk(KERN_CRIT "How did I get here?\n");
 		return -EINVAL;
 
 	case MIPS_FIXADE:
-		tmp = current->thread.mflags & ~3;
-		current->thread.mflags = tmp | (arg1 & 3);
+		if (arg1 & ~3)
+			return -EINVAL;
+
+		if (arg1 & 1)
+			set_thread_flag(TIF_FIXADE);
+		else
+			clear_thread_flag(TIF_FIXADE);
+		if (arg1 & 2)
+			set_thread_flag(TIF_LOGADE);
+		else
+			clear_thread_flag(TIF_FIXADE);
+
 		return 0;
 
 	case FLUSH_CACHE:

arch/mips/kernel/traps.c

@@ -775,7 +775,7 @@ static void mt_ase_fp_affinity(void)
 			cpus_and(tmask, current->thread.user_cpus_allowed,
 			         mt_fpu_cpumask);
 			set_cpus_allowed(current, tmask);
-			current->thread.mflags |= MF_FPUBOUND;
+			set_thread_flag(TIF_FPUBOUND);
 		}
 	}
 #endif /* CONFIG_MIPS_MT_FPAFF */