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@@ -56,7 +56,7 @@ struct cpuinfo_mips {
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struct cache_desc tcache; /* Tertiary/split secondary cache */
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int srsets; /* Shadow register sets */
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int core; /* physical core number */
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-#if defined(CONFIG_MIPS_MT_SMTC)
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+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
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/*
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* In the MIPS MT "SMTC" model, each TC is considered
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* to be a "CPU" for the purposes of scheduling, but
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@@ -64,7 +64,7 @@ struct cpuinfo_mips {
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* to all TCs within the same VPE.
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*/
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int vpe_id; /* Virtual Processor number */
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-#endif /* CONFIG_MIPS_MT */
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+#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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int tc_id; /* Thread Context number */
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#endif
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