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@@ -654,16 +654,19 @@ static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
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snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
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SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
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SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
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+
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+ /* if using pll, clk_ctrl must be set after pll power up */
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+ snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
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} else {
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+ /* otherwise, clk_ctrl must be set before pll power down */
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+ snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
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+
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/* power down pll */
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snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
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SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
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0);
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}
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- /* if using pll, clk_ctrl must be set after pll power up */
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- snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
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-
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return 0;
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}
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@@ -1480,6 +1483,7 @@ static struct snd_soc_codec_driver sgtl5000_driver = {
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static const struct regmap_config sgtl5000_regmap = {
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.reg_bits = 16,
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.val_bits = 16,
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+ .reg_stride = 2,
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.max_register = SGTL5000_MAX_REG_OFFSET,
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.volatile_reg = sgtl5000_volatile,
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