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@@ -71,21 +71,12 @@
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#define PCH_REC 0x00007f00
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#define PCH_TEC 0x000000ff
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+
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#define PCH_TX_OK BIT(3)
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#define PCH_RX_OK BIT(4)
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#define PCH_EPASSIV BIT(5)
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#define PCH_EWARN BIT(6)
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#define PCH_BUS_OFF BIT(7)
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-#define PCH_LEC0 BIT(0)
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-#define PCH_LEC1 BIT(1)
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-#define PCH_LEC2 BIT(2)
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-#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
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-#define PCH_STUF_ERR PCH_LEC0
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-#define PCH_FORM_ERR PCH_LEC1
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-#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1)
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-#define PCH_BIT1_ERR PCH_LEC2
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-#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2)
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-#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
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/* bit position of certain controller bits. */
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#define PCH_BIT_BRP 0
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@@ -117,6 +108,16 @@ enum pch_ifreg {
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PCH_TX_IFREG,
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};
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+enum pch_can_err {
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+ PCH_STUF_ERR = 1,
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+ PCH_FORM_ERR,
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+ PCH_ACK_ERR,
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+ PCH_BIT1_ERR,
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+ PCH_BIT0_ERR,
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+ PCH_CRC_ERR,
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+ PCH_LEC_ALL,
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+};
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+
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enum pch_can_mode {
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PCH_CAN_ENABLE,
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PCH_CAN_DISABLE,
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@@ -620,7 +621,7 @@ static void pch_can_error(struct net_device *ndev, u32 status)
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struct sk_buff *skb;
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struct pch_can_priv *priv = netdev_priv(ndev);
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struct can_frame *cf;
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- u32 errc;
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+ u32 errc, lec;
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struct net_device_stats *stats = &(priv->ndev->stats);
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enum can_state state = priv->can.state;
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@@ -665,33 +666,37 @@ static void pch_can_error(struct net_device *ndev, u32 status)
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"%s -> CAN controller is ERROR PASSIVE .\n", __func__);
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}
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- if (status & PCH_LEC_ALL) {
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+ lec = status & PCH_LEC_ALL;
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+ switch (lec) {
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+ case PCH_STUF_ERR:
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+ cf->data[2] |= CAN_ERR_PROT_STUFF;
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priv->can.can_stats.bus_error++;
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stats->rx_errors++;
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- switch (status & PCH_LEC_ALL) {
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- case PCH_STUF_ERR:
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- cf->data[2] |= CAN_ERR_PROT_STUFF;
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- break;
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- case PCH_FORM_ERR:
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- cf->data[2] |= CAN_ERR_PROT_FORM;
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- break;
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- case PCH_ACK_ERR:
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- cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
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- CAN_ERR_PROT_LOC_ACK_DEL;
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- break;
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- case PCH_BIT1_ERR:
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- case PCH_BIT0_ERR:
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- cf->data[2] |= CAN_ERR_PROT_BIT;
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- break;
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- case PCH_CRC_ERR:
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- cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
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- CAN_ERR_PROT_LOC_CRC_DEL;
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- break;
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- default:
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- iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
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- break;
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- }
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-
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+ break;
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+ case PCH_FORM_ERR:
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+ cf->data[2] |= CAN_ERR_PROT_FORM;
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+ priv->can.can_stats.bus_error++;
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+ stats->rx_errors++;
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+ break;
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+ case PCH_ACK_ERR:
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+ cf->can_id |= CAN_ERR_ACK;
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+ priv->can.can_stats.bus_error++;
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+ stats->rx_errors++;
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+ break;
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+ case PCH_BIT1_ERR:
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+ case PCH_BIT0_ERR:
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+ cf->data[2] |= CAN_ERR_PROT_BIT;
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+ priv->can.can_stats.bus_error++;
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+ stats->rx_errors++;
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+ break;
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+ case PCH_CRC_ERR:
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+ cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
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+ CAN_ERR_PROT_LOC_CRC_DEL;
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+ priv->can.can_stats.bus_error++;
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+ stats->rx_errors++;
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+ break;
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+ case PCH_LEC_ALL: /* Written by CPU. No error status */
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+ break;
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}
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priv->can.state = state;
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