|
@@ -14,13 +14,13 @@
|
|
|
#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
|
|
|
#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
|
|
|
|
|
|
-#define ATH724X_PCI_DEV_BASE 0x14000000
|
|
|
-#define ATH724X_PCI_MEM_BASE 0x10000000
|
|
|
-#define ATH724X_PCI_MEM_SIZE 0x08000000
|
|
|
+#define AR724X_PCI_DEV_BASE 0x14000000
|
|
|
+#define AR724X_PCI_MEM_BASE 0x10000000
|
|
|
+#define AR724X_PCI_MEM_SIZE 0x08000000
|
|
|
|
|
|
-static DEFINE_SPINLOCK(ath724x_pci_lock);
|
|
|
+static DEFINE_SPINLOCK(ar724x_pci_lock);
|
|
|
|
|
|
-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
+static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
int size, uint32_t *value)
|
|
|
{
|
|
|
unsigned long flags, addr, tval, mask;
|
|
@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
if (where & (size - 1))
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
|
|
- spin_lock_irqsave(&ath724x_pci_lock, flags);
|
|
|
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
|
|
|
|
|
|
switch (size) {
|
|
|
case 1:
|
|
|
addr = where & ~3;
|
|
|
mask = 0xff000000 >> ((where % 4) * 8);
|
|
|
- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
|
|
+ tval = reg_read(AR724X_PCI_DEV_BASE + addr);
|
|
|
tval = tval & ~mask;
|
|
|
*value = (tval >> ((4 - (where % 4))*8));
|
|
|
break;
|
|
|
case 2:
|
|
|
addr = where & ~3;
|
|
|
mask = 0xffff0000 >> ((where % 4)*8);
|
|
|
- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
|
|
+ tval = reg_read(AR724X_PCI_DEV_BASE + addr);
|
|
|
tval = tval & ~mask;
|
|
|
*value = (tval >> ((4 - (where % 4))*8));
|
|
|
break;
|
|
|
case 4:
|
|
|
- *value = reg_read(ATH724X_PCI_DEV_BASE + where);
|
|
|
+ *value = reg_read(AR724X_PCI_DEV_BASE + where);
|
|
|
break;
|
|
|
default:
|
|
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
|
|
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
|
|
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
}
|
|
|
|
|
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
|
|
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
}
|
|
|
|
|
|
-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
+static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
int size, uint32_t value)
|
|
|
{
|
|
|
unsigned long flags, tval, addr, mask;
|
|
@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
if (where & (size - 1))
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
|
|
- spin_lock_irqsave(&ath724x_pci_lock, flags);
|
|
|
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
|
|
|
|
|
|
switch (size) {
|
|
|
case 1:
|
|
|
- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
|
|
+ addr = (AR724X_PCI_DEV_BASE + where) & ~3;
|
|
|
mask = 0xff000000 >> ((where % 4)*8);
|
|
|
tval = reg_read(addr);
|
|
|
tval = tval & ~mask;
|
|
@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
reg_write(addr, tval);
|
|
|
break;
|
|
|
case 2:
|
|
|
- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
|
|
+ addr = (AR724X_PCI_DEV_BASE + where) & ~3;
|
|
|
mask = 0xffff0000 >> ((where % 4)*8);
|
|
|
tval = reg_read(addr);
|
|
|
tval = tval & ~mask;
|
|
@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
|
|
reg_write(addr, tval);
|
|
|
break;
|
|
|
case 4:
|
|
|
- reg_write((ATH724X_PCI_DEV_BASE + where), value);
|
|
|
+ reg_write((AR724X_PCI_DEV_BASE + where), value);
|
|
|
break;
|
|
|
default:
|
|
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
|
|
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
|
|
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
}
|
|
|
|
|
|
- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
|
|
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
}
|
|
|
|
|
|
-static struct pci_ops ath724x_pci_ops = {
|
|
|
- .read = ath724x_pci_read,
|
|
|
- .write = ath724x_pci_write,
|
|
|
+static struct pci_ops ar724x_pci_ops = {
|
|
|
+ .read = ar724x_pci_read,
|
|
|
+ .write = ar724x_pci_write,
|
|
|
};
|
|
|
|
|
|
-static struct resource ath724x_io_resource = {
|
|
|
+static struct resource ar724x_io_resource = {
|
|
|
.name = "PCI IO space",
|
|
|
.start = 0,
|
|
|
.end = 0,
|
|
|
.flags = IORESOURCE_IO,
|
|
|
};
|
|
|
|
|
|
-static struct resource ath724x_mem_resource = {
|
|
|
+static struct resource ar724x_mem_resource = {
|
|
|
.name = "PCI memory space",
|
|
|
- .start = ATH724X_PCI_MEM_BASE,
|
|
|
- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
|
|
|
+ .start = AR724X_PCI_MEM_BASE,
|
|
|
+ .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
};
|
|
|
|
|
|
-static struct pci_controller ath724x_pci_controller = {
|
|
|
- .pci_ops = &ath724x_pci_ops,
|
|
|
- .io_resource = &ath724x_io_resource,
|
|
|
- .mem_resource = &ath724x_mem_resource,
|
|
|
+static struct pci_controller ar724x_pci_controller = {
|
|
|
+ .pci_ops = &ar724x_pci_ops,
|
|
|
+ .io_resource = &ar724x_io_resource,
|
|
|
+ .mem_resource = &ar724x_mem_resource,
|
|
|
};
|
|
|
|
|
|
-int __init ath724x_pcibios_init(void)
|
|
|
+int __init ar724x_pcibios_init(void)
|
|
|
{
|
|
|
- register_pci_controller(&ath724x_pci_controller);
|
|
|
+ register_pci_controller(&ar724x_pci_controller);
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
}
|