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@@ -190,6 +190,7 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
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/* minimum number of free TX descriptors required to wake up TX process */
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/* minimum number of free TX descriptors required to wake up TX process */
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#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
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#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
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+#define TG3_TX_BD_DMA_MAX 4096
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#define TG3_RAW_IP_ALIGN 2
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#define TG3_RAW_IP_ALIGN 2
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@@ -4824,7 +4825,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
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txq = netdev_get_tx_queue(tp->dev, index);
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txq = netdev_get_tx_queue(tp->dev, index);
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while (sw_idx != hw_idx) {
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while (sw_idx != hw_idx) {
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- struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
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+ struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
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struct sk_buff *skb = ri->skb;
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struct sk_buff *skb = ri->skb;
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int i, tx_bug = 0;
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int i, tx_bug = 0;
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@@ -4840,6 +4841,12 @@ static void tg3_tx(struct tg3_napi *tnapi)
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ri->skb = NULL;
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ri->skb = NULL;
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+ while (ri->fragmented) {
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+ ri->fragmented = false;
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+ sw_idx = NEXT_TX(sw_idx);
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+ ri = &tnapi->tx_buffers[sw_idx];
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+ }
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+
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sw_idx = NEXT_TX(sw_idx);
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sw_idx = NEXT_TX(sw_idx);
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for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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@@ -4851,6 +4858,13 @@ static void tg3_tx(struct tg3_napi *tnapi)
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dma_unmap_addr(ri, mapping),
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dma_unmap_addr(ri, mapping),
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skb_shinfo(skb)->frags[i].size,
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skb_shinfo(skb)->frags[i].size,
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PCI_DMA_TODEVICE);
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PCI_DMA_TODEVICE);
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+
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+ while (ri->fragmented) {
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+ ri->fragmented = false;
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+ sw_idx = NEXT_TX(sw_idx);
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+ ri = &tnapi->tx_buffers[sw_idx];
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+ }
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+
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sw_idx = NEXT_TX(sw_idx);
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sw_idx = NEXT_TX(sw_idx);
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}
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}
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@@ -5901,40 +5915,100 @@ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
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#endif
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#endif
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}
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}
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-static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
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- dma_addr_t mapping, int len, u32 flags,
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- u32 mss_and_is_end)
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+static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
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+ dma_addr_t mapping, u32 len, u32 flags,
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+ u32 mss, u32 vlan)
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+{
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+ txbd->addr_hi = ((u64) mapping >> 32);
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+ txbd->addr_lo = ((u64) mapping & 0xffffffff);
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+ txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
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+ txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
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+}
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+
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+static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
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+ dma_addr_t map, u32 len, u32 flags,
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+ u32 mss, u32 vlan)
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{
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{
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- struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
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- int is_end = (mss_and_is_end & 0x1);
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- u32 mss = (mss_and_is_end >> 1);
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- u32 vlan_tag = 0;
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+ struct tg3 *tp = tnapi->tp;
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+ bool hwbug = false;
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+
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+ if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
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+ hwbug = 1;
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+
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+ if (tg3_4g_overflow_test(map, len))
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+ hwbug = 1;
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+
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+ if (tg3_40bit_overflow_test(tp, map, len))
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+ hwbug = 1;
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+
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+ if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
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+ u32 tmp_flag = flags & ~TXD_FLAG_END;
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+ while (len > TG3_TX_BD_DMA_MAX) {
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+ u32 frag_len = TG3_TX_BD_DMA_MAX;
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+ len -= TG3_TX_BD_DMA_MAX;
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+
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+ if (len) {
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+ tnapi->tx_buffers[*entry].fragmented = true;
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+ /* Avoid the 8byte DMA problem */
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+ if (len <= 8) {
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+ len += TG3_TX_BD_DMA_MAX / 2;
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+ frag_len = TG3_TX_BD_DMA_MAX / 2;
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+ }
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+ } else
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+ tmp_flag = flags;
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+
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+ if (*budget) {
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+ tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
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+ frag_len, tmp_flag, mss, vlan);
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+ (*budget)--;
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+ *entry = NEXT_TX(*entry);
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+ } else {
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+ hwbug = 1;
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+ break;
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+ }
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+
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+ map += frag_len;
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+ }
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- if (is_end)
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- flags |= TXD_FLAG_END;
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- if (flags & TXD_FLAG_VLAN) {
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- vlan_tag = flags >> 16;
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- flags &= 0xffff;
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+ if (len) {
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+ if (*budget) {
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+ tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
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+ len, flags, mss, vlan);
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+ (*budget)--;
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+ *entry = NEXT_TX(*entry);
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+ } else {
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+ hwbug = 1;
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+ }
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+ }
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+ } else {
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+ tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
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+ len, flags, mss, vlan);
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+ *entry = NEXT_TX(*entry);
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}
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}
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- vlan_tag |= (mss << TXD_MSS_SHIFT);
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- txd->addr_hi = ((u64) mapping >> 32);
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- txd->addr_lo = ((u64) mapping & 0xffffffff);
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- txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
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- txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
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+ return hwbug;
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}
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}
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-static void tg3_skb_error_unmap(struct tg3_napi *tnapi,
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- struct sk_buff *skb, int last)
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+static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
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{
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{
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int i;
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int i;
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- u32 entry = tnapi->tx_prod;
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- struct ring_info *txb = &tnapi->tx_buffers[entry];
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+ struct sk_buff *skb;
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+ struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
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+
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+ skb = txb->skb;
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+ txb->skb = NULL;
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pci_unmap_single(tnapi->tp->pdev,
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pci_unmap_single(tnapi->tp->pdev,
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dma_unmap_addr(txb, mapping),
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dma_unmap_addr(txb, mapping),
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skb_headlen(skb),
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skb_headlen(skb),
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PCI_DMA_TODEVICE);
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PCI_DMA_TODEVICE);
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+
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+ while (txb->fragmented) {
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+ txb->fragmented = false;
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+ entry = NEXT_TX(entry);
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+ txb = &tnapi->tx_buffers[entry];
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+ }
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+
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for (i = 0; i < last; i++) {
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for (i = 0; i < last; i++) {
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skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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@@ -5944,18 +6018,24 @@ static void tg3_skb_error_unmap(struct tg3_napi *tnapi,
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pci_unmap_page(tnapi->tp->pdev,
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pci_unmap_page(tnapi->tp->pdev,
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dma_unmap_addr(txb, mapping),
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dma_unmap_addr(txb, mapping),
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frag->size, PCI_DMA_TODEVICE);
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frag->size, PCI_DMA_TODEVICE);
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+
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+ while (txb->fragmented) {
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+ txb->fragmented = false;
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+ entry = NEXT_TX(entry);
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+ txb = &tnapi->tx_buffers[entry];
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+ }
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}
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}
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}
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}
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/* Workaround 4GB and 40-bit hardware DMA bugs. */
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/* Workaround 4GB and 40-bit hardware DMA bugs. */
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static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
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static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
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struct sk_buff *skb,
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struct sk_buff *skb,
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- u32 base_flags, u32 mss)
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+ u32 *entry, u32 *budget,
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+ u32 base_flags, u32 mss, u32 vlan)
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{
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{
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struct tg3 *tp = tnapi->tp;
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struct tg3 *tp = tnapi->tp;
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struct sk_buff *new_skb;
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struct sk_buff *new_skb;
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dma_addr_t new_addr = 0;
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dma_addr_t new_addr = 0;
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- u32 entry = tnapi->tx_prod;
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int ret = 0;
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int ret = 0;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
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@@ -5976,24 +6056,22 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
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PCI_DMA_TODEVICE);
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PCI_DMA_TODEVICE);
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/* Make sure the mapping succeeded */
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/* Make sure the mapping succeeded */
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if (pci_dma_mapping_error(tp->pdev, new_addr)) {
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if (pci_dma_mapping_error(tp->pdev, new_addr)) {
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- ret = -1;
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dev_kfree_skb(new_skb);
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dev_kfree_skb(new_skb);
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-
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- /* Make sure new skb does not cross any 4G boundaries.
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- * Drop the packet if it does.
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- */
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- } else if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
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- pci_unmap_single(tp->pdev, new_addr, new_skb->len,
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- PCI_DMA_TODEVICE);
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ret = -1;
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ret = -1;
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- dev_kfree_skb(new_skb);
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} else {
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} else {
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- tnapi->tx_buffers[entry].skb = new_skb;
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- dma_unmap_addr_set(&tnapi->tx_buffers[entry],
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+ base_flags |= TXD_FLAG_END;
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+
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+ tnapi->tx_buffers[*entry].skb = new_skb;
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+ dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
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mapping, new_addr);
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mapping, new_addr);
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- tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
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- base_flags, 1 | (mss << 1));
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+ if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
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+ new_skb->len, base_flags,
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+ mss, vlan)) {
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+ tg3_tx_skb_unmap(tnapi, *entry, 0);
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+ dev_kfree_skb(new_skb);
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+ ret = -1;
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+ }
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}
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}
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}
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}
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@@ -6051,7 +6129,8 @@ tg3_tso_bug_end:
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static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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{
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struct tg3 *tp = netdev_priv(dev);
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struct tg3 *tp = netdev_priv(dev);
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- u32 len, entry, base_flags, mss;
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+ u32 len, entry, base_flags, mss, vlan = 0;
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+ u32 budget;
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int i = -1, would_hit_hwbug;
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int i = -1, would_hit_hwbug;
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dma_addr_t mapping;
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dma_addr_t mapping;
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struct tg3_napi *tnapi;
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struct tg3_napi *tnapi;
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@@ -6063,12 +6142,14 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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if (tg3_flag(tp, ENABLE_TSS))
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if (tg3_flag(tp, ENABLE_TSS))
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tnapi++;
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tnapi++;
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+ budget = tg3_tx_avail(tnapi);
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+
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/* We are running in BH disabled context with netif_tx_lock
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/* We are running in BH disabled context with netif_tx_lock
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* and TX reclaim runs via tp->napi.poll inside of a software
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* and TX reclaim runs via tp->napi.poll inside of a software
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* interrupt. Furthermore, IRQ processing runs lockless so we have
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* interrupt. Furthermore, IRQ processing runs lockless so we have
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* no IRQ context deadlocks to worry about either. Rejoice!
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* no IRQ context deadlocks to worry about either. Rejoice!
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*/
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*/
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- if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
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+ if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
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if (!netif_tx_queue_stopped(txq)) {
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if (!netif_tx_queue_stopped(txq)) {
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netif_tx_stop_queue(txq);
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netif_tx_stop_queue(txq);
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@@ -6153,9 +6234,12 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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}
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}
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}
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}
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- if (vlan_tx_tag_present(skb))
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- base_flags |= (TXD_FLAG_VLAN |
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- (vlan_tx_tag_get(skb) << 16));
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+#ifdef BCM_KERNEL_SUPPORTS_8021Q
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+ if (vlan_tx_tag_present(skb)) {
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+ base_flags |= TXD_FLAG_VLAN;
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+ vlan = vlan_tx_tag_get(skb);
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+ }
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+#endif
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if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
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if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
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!mss && skb->len > VLAN_ETH_FRAME_LEN)
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!mss && skb->len > VLAN_ETH_FRAME_LEN)
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@@ -6174,25 +6258,23 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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would_hit_hwbug = 0;
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would_hit_hwbug = 0;
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- if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
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- would_hit_hwbug = 1;
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-
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- if (tg3_4g_overflow_test(mapping, len))
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- would_hit_hwbug = 1;
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-
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- if (tg3_40bit_overflow_test(tp, mapping, len))
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- would_hit_hwbug = 1;
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-
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if (tg3_flag(tp, 5701_DMA_BUG))
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if (tg3_flag(tp, 5701_DMA_BUG))
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would_hit_hwbug = 1;
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would_hit_hwbug = 1;
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- tg3_set_txd(tnapi, entry, mapping, len, base_flags,
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- (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
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-
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- entry = NEXT_TX(entry);
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+ if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
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+ ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
|
|
|
|
+ mss, vlan))
|
|
|
|
+ would_hit_hwbug = 1;
|
|
|
|
|
|
/* Now loop through additional data fragments, and queue them. */
|
|
/* Now loop through additional data fragments, and queue them. */
|
|
if (skb_shinfo(skb)->nr_frags > 0) {
|
|
if (skb_shinfo(skb)->nr_frags > 0) {
|
|
|
|
+ u32 tmp_mss = mss;
|
|
|
|
+
|
|
|
|
+ if (!tg3_flag(tp, HW_TSO_1) &&
|
|
|
|
+ !tg3_flag(tp, HW_TSO_2) &&
|
|
|
|
+ !tg3_flag(tp, HW_TSO_3))
|
|
|
|
+ tmp_mss = 0;
|
|
|
|
+
|
|
last = skb_shinfo(skb)->nr_frags - 1;
|
|
last = skb_shinfo(skb)->nr_frags - 1;
|
|
for (i = 0; i <= last; i++) {
|
|
for (i = 0; i <= last; i++) {
|
|
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
|
|
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
|
|
@@ -6209,39 +6291,25 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
if (pci_dma_mapping_error(tp->pdev, mapping))
|
|
if (pci_dma_mapping_error(tp->pdev, mapping))
|
|
goto dma_error;
|
|
goto dma_error;
|
|
|
|
|
|
- if (tg3_flag(tp, SHORT_DMA_BUG) &&
|
|
|
|
- len <= 8)
|
|
|
|
|
|
+ if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
|
|
|
|
+ len, base_flags |
|
|
|
|
+ ((i == last) ? TXD_FLAG_END : 0),
|
|
|
|
+ tmp_mss, vlan))
|
|
would_hit_hwbug = 1;
|
|
would_hit_hwbug = 1;
|
|
-
|
|
|
|
- if (tg3_4g_overflow_test(mapping, len))
|
|
|
|
- would_hit_hwbug = 1;
|
|
|
|
-
|
|
|
|
- if (tg3_40bit_overflow_test(tp, mapping, len))
|
|
|
|
- would_hit_hwbug = 1;
|
|
|
|
-
|
|
|
|
- if (tg3_flag(tp, HW_TSO_1) ||
|
|
|
|
- tg3_flag(tp, HW_TSO_2) ||
|
|
|
|
- tg3_flag(tp, HW_TSO_3))
|
|
|
|
- tg3_set_txd(tnapi, entry, mapping, len,
|
|
|
|
- base_flags, (i == last)|(mss << 1));
|
|
|
|
- else
|
|
|
|
- tg3_set_txd(tnapi, entry, mapping, len,
|
|
|
|
- base_flags, (i == last));
|
|
|
|
-
|
|
|
|
- entry = NEXT_TX(entry);
|
|
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
if (would_hit_hwbug) {
|
|
if (would_hit_hwbug) {
|
|
- tg3_skb_error_unmap(tnapi, skb, i);
|
|
|
|
|
|
+ tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
|
|
|
|
|
|
/* If the workaround fails due to memory/mapping
|
|
/* If the workaround fails due to memory/mapping
|
|
* failure, silently drop this packet.
|
|
* failure, silently drop this packet.
|
|
*/
|
|
*/
|
|
- if (tigon3_dma_hwbug_workaround(tnapi, skb, base_flags, mss))
|
|
|
|
|
|
+ entry = tnapi->tx_prod;
|
|
|
|
+ budget = tg3_tx_avail(tnapi);
|
|
|
|
+ if (tigon3_dma_hwbug_workaround(tnapi, skb, &entry, &budget,
|
|
|
|
+ base_flags, mss, vlan))
|
|
goto out_unlock;
|
|
goto out_unlock;
|
|
-
|
|
|
|
- entry = NEXT_TX(tnapi->tx_prod);
|
|
|
|
}
|
|
}
|
|
|
|
|
|
skb_tx_timestamp(skb);
|
|
skb_tx_timestamp(skb);
|
|
@@ -6269,7 +6337,7 @@ out_unlock:
|
|
return NETDEV_TX_OK;
|
|
return NETDEV_TX_OK;
|
|
|
|
|
|
dma_error:
|
|
dma_error:
|
|
- tg3_skb_error_unmap(tnapi, skb, i);
|
|
|
|
|
|
+ tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
|
|
dev_kfree_skb(skb);
|
|
dev_kfree_skb(skb);
|
|
tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
|
|
tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
|
|
return NETDEV_TX_OK;
|
|
return NETDEV_TX_OK;
|
|
@@ -6602,35 +6670,13 @@ static void tg3_free_rings(struct tg3 *tp)
|
|
if (!tnapi->tx_buffers)
|
|
if (!tnapi->tx_buffers)
|
|
continue;
|
|
continue;
|
|
|
|
|
|
- for (i = 0; i < TG3_TX_RING_SIZE; ) {
|
|
|
|
- struct ring_info *txp;
|
|
|
|
- struct sk_buff *skb;
|
|
|
|
- unsigned int k;
|
|
|
|
-
|
|
|
|
- txp = &tnapi->tx_buffers[i];
|
|
|
|
- skb = txp->skb;
|
|
|
|
|
|
+ for (i = 0; i < TG3_TX_RING_SIZE; i++) {
|
|
|
|
+ struct sk_buff *skb = tnapi->tx_buffers[i].skb;
|
|
|
|
|
|
- if (skb == NULL) {
|
|
|
|
- i++;
|
|
|
|
|
|
+ if (!skb)
|
|
continue;
|
|
continue;
|
|
- }
|
|
|
|
-
|
|
|
|
- pci_unmap_single(tp->pdev,
|
|
|
|
- dma_unmap_addr(txp, mapping),
|
|
|
|
- skb_headlen(skb),
|
|
|
|
- PCI_DMA_TODEVICE);
|
|
|
|
- txp->skb = NULL;
|
|
|
|
|
|
|
|
- i++;
|
|
|
|
-
|
|
|
|
- for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
|
|
|
|
- txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
|
|
|
|
- pci_unmap_page(tp->pdev,
|
|
|
|
- dma_unmap_addr(txp, mapping),
|
|
|
|
- skb_shinfo(skb)->frags[k].size,
|
|
|
|
- PCI_DMA_TODEVICE);
|
|
|
|
- i++;
|
|
|
|
- }
|
|
|
|
|
|
+ tg3_tx_skb_unmap(tnapi, i, skb_shinfo(skb)->nr_frags);
|
|
|
|
|
|
dev_kfree_skb_any(skb);
|
|
dev_kfree_skb_any(skb);
|
|
}
|
|
}
|
|
@@ -6762,9 +6808,9 @@ static int tg3_alloc_consistent(struct tg3 *tp)
|
|
*/
|
|
*/
|
|
if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
|
|
if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
|
|
(i && tg3_flag(tp, ENABLE_TSS))) {
|
|
(i && tg3_flag(tp, ENABLE_TSS))) {
|
|
- tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
|
|
|
|
- TG3_TX_RING_SIZE,
|
|
|
|
- GFP_KERNEL);
|
|
|
|
|
|
+ tnapi->tx_buffers = kzalloc(
|
|
|
|
+ sizeof(struct tg3_tx_ring_info) *
|
|
|
|
+ TG3_TX_RING_SIZE, GFP_KERNEL);
|
|
if (!tnapi->tx_buffers)
|
|
if (!tnapi->tx_buffers)
|
|
goto err_out;
|
|
goto err_out;
|
|
|
|
|
|
@@ -8360,7 +8406,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
|
|
/* Program the jumbo buffer descriptor ring control
|
|
/* Program the jumbo buffer descriptor ring control
|
|
* blocks on those devices that have them.
|
|
* blocks on those devices that have them.
|
|
*/
|
|
*/
|
|
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
|
|
|
|
|
|
+ if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
|
|
(tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
|
|
(tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
|
|
|
|
|
|
if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
|
|
if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
|
|
@@ -11204,6 +11250,7 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
|
|
{
|
|
{
|
|
u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
|
|
u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
|
|
u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
|
|
u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
|
|
|
|
+ u32 budget;
|
|
struct sk_buff *skb, *rx_skb;
|
|
struct sk_buff *skb, *rx_skb;
|
|
u8 *tx_data;
|
|
u8 *tx_data;
|
|
dma_addr_t map;
|
|
dma_addr_t map;
|
|
@@ -11363,6 +11410,10 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
|
|
return -EIO;
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+ val = tnapi->tx_prod;
|
|
|
|
+ tnapi->tx_buffers[val].skb = skb;
|
|
|
|
+ dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
|
|
|
|
+
|
|
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
|
|
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
|
|
rnapi->coal_now);
|
|
rnapi->coal_now);
|
|
|
|
|
|
@@ -11370,8 +11421,13 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
|
|
|
|
|
|
rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
|
|
rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
|
|
|
|
|
|
- tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len,
|
|
|
|
- base_flags, (mss << 1) | 1);
|
|
|
|
|
|
+ budget = tg3_tx_avail(tnapi);
|
|
|
|
+ if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
|
|
|
|
+ base_flags | TXD_FLAG_END, mss, 0)) {
|
|
|
|
+ tnapi->tx_buffers[val].skb = NULL;
|
|
|
|
+ dev_kfree_skb(skb);
|
|
|
|
+ return -EIO;
|
|
|
|
+ }
|
|
|
|
|
|
tnapi->tx_prod++;
|
|
tnapi->tx_prod++;
|
|
|
|
|
|
@@ -11394,7 +11450,7 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
|
|
break;
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
- pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
|
|
|
|
|
|
+ tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, 0);
|
|
dev_kfree_skb(skb);
|
|
dev_kfree_skb(skb);
|
|
|
|
|
|
if (tx_idx != tnapi->tx_prod)
|
|
if (tx_idx != tnapi->tx_prod)
|
|
@@ -13817,7 +13873,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
|
|
tg3_flag_set(tp, 5705_PLUS);
|
|
tg3_flag_set(tp, 5705_PLUS);
|
|
|
|
|
|
/* Determine TSO capabilities */
|
|
/* Determine TSO capabilities */
|
|
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
|
|
|
|
|
|
+ if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
|
|
; /* Do nothing. HW bug. */
|
|
; /* Do nothing. HW bug. */
|
|
else if (tg3_flag(tp, 57765_PLUS))
|
|
else if (tg3_flag(tp, 57765_PLUS))
|
|
tg3_flag_set(tp, HW_TSO_3);
|
|
tg3_flag_set(tp, HW_TSO_3);
|
|
@@ -13880,11 +13936,14 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
|
|
if (tg3_flag(tp, 5755_PLUS))
|
|
if (tg3_flag(tp, 5755_PLUS))
|
|
tg3_flag_set(tp, SHORT_DMA_BUG);
|
|
tg3_flag_set(tp, SHORT_DMA_BUG);
|
|
|
|
|
|
|
|
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
|
|
|
|
+ tg3_flag_set(tp, 4K_FIFO_LIMIT);
|
|
|
|
+
|
|
if (tg3_flag(tp, 5717_PLUS))
|
|
if (tg3_flag(tp, 5717_PLUS))
|
|
tg3_flag_set(tp, LRG_PROD_RING_CAP);
|
|
tg3_flag_set(tp, LRG_PROD_RING_CAP);
|
|
|
|
|
|
if (tg3_flag(tp, 57765_PLUS) &&
|
|
if (tg3_flag(tp, 57765_PLUS) &&
|
|
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
|
|
|
|
|
|
+ tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
|
|
tg3_flag_set(tp, USE_JUMBO_BDFLAG);
|
|
tg3_flag_set(tp, USE_JUMBO_BDFLAG);
|
|
|
|
|
|
if (!tg3_flag(tp, 5705_PLUS) ||
|
|
if (!tg3_flag(tp, 5705_PLUS) ||
|