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@@ -62,6 +62,7 @@ void irq_gc_mask_set_bit(struct irq_data *d)
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irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
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irq_gc_unlock(gc);
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}
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+EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
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/**
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* irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
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@@ -81,6 +82,7 @@ void irq_gc_mask_clr_bit(struct irq_data *d)
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irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
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irq_gc_unlock(gc);
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}
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+EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
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/**
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* irq_gc_unmask_enable_reg - Unmask chip via enable register
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@@ -115,6 +117,7 @@ void irq_gc_ack_set_bit(struct irq_data *d)
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irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
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irq_gc_unlock(gc);
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}
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+EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
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/**
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* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
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