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+/*
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+ * bonito board support
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+ *
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+ * Copyright (C) 2011 Renesas Solutions Corp.
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+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/interrupt.h>
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+#include <linux/irq.h>
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+#include <linux/platform_device.h>
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+#include <linux/gpio.h>
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+#include <mach/common.h>
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+#include <asm/mach-types.h>
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+#include <asm/mach/arch.h>
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+#include <asm/mach/map.h>
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+#include <asm/mach/time.h>
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+#include <asm/hardware/cache-l2x0.h>
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+#include <mach/r8a7740.h>
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+
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+/*
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+ * CS Address device note
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+ *----------------------------------------------------------------
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+ * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
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+ * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
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+ * 4 -
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+ * 5A -
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+ * 5B 0x1600_0000 SRAM (8MB)
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+ * 6 0x1800_0000 FPGA (64K)
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+ * 0x1801_0000 Ether (4KB)
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+ * 0x1801_1000 USB (4KB)
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+ */
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+
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+/*
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+ * SW12
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+ *
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+ * bit1 bit2 bit3
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+ *----------------------------------------------------------------------------
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+ * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
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+ * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
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+ */
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+
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+/*
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+ * FPGA
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+ */
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+#define A1MDSR 0x10E0
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+#define BVERR 0x1100
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+static u16 bonito_fpga_read(u32 offset)
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+{
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+ return __raw_readw(0xf0003000 + offset);
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+}
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+
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+static void bonito_fpga_write(u32 offset, u16 val)
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+{
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+ __raw_writew(val, 0xf0003000 + offset);
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+}
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+
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+/*
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+ * devices
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+ */
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+static struct platform_device *bonito_devices[] __initdata = {
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+};
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+
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+/*
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+ * map I/O
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+ */
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+static struct map_desc bonito_io_desc[] __initdata = {
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+ /*
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+ * for CPGA/INTC/PFC
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+ * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
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+ */
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+ {
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+ .virtual = 0xe6000000,
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+ .pfn = __phys_to_pfn(0xe6000000),
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+ .length = 160 << 20,
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+ .type = MT_DEVICE_NONSHARED
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+ },
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+#ifdef CONFIG_CACHE_L2X0
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+ /*
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+ * for l2x0_init()
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+ * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
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+ */
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+ {
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+ .virtual = 0xf0002000,
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+ .pfn = __phys_to_pfn(0xf0100000),
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+ .length = PAGE_SIZE,
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+ .type = MT_DEVICE_NONSHARED
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+ },
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+#endif
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+ /*
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+ * for FPGA (0x1800000-0x19ffffff)
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+ * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
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+ */
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+ {
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+ .virtual = 0xf0003000,
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+ .pfn = __phys_to_pfn(0x18000000),
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+ .length = PAGE_SIZE * 2,
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+ .type = MT_DEVICE_NONSHARED
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+ }
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+};
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+
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+static void __init bonito_map_io(void)
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+{
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+ iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
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+
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+ /* setup early devices and console here as well */
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+ r8a7740_add_early_devices();
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+ shmobile_setup_console();
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+}
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+
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+/*
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+ * board init
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+ */
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+static void __init bonito_init(void)
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+{
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+ u16 val;
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+
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+ r8a7740_pinmux_init();
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+
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+ /* FPGA */
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+ gpio_request(GPIO_FN_CS5B, NULL);
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+ gpio_request(GPIO_FN_CS6A, NULL);
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+ gpio_request(GPIO_FN_CS5A_PORT105, NULL);
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+ gpio_request(GPIO_FN_IRQ10, NULL);
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+
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+ val = bonito_fpga_read(BVERR);
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+ pr_info("bonito version: cpu %02x, base %02x\n",
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+ ((val >> 8) & 0xFF),
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+ ((val >> 0) & 0xFF));
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+
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+ /* SCIFA5 */
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+ gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
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+ gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
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+
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+#ifdef CONFIG_CACHE_L2X0
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+ /* Early BRESP enable, Shared attribute override enable, 32K*8way */
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+ l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
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+#endif
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+
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+ r8a7740_add_standard_devices();
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+ platform_add_devices(bonito_devices, ARRAY_SIZE(bonito_devices));
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+}
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+
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+static void __init bonito_timer_init(void)
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+{
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+ u16 val;
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+ u8 md_ck = 0;
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+
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+ /* read MD_CK value */
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+ val = bonito_fpga_read(A1MDSR);
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+ if (val & (1 << 10))
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+ md_ck |= MD_CK2;
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+ if (val & (1 << 9))
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+ md_ck |= MD_CK1;
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+ if (val & (1 << 8))
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+ md_ck |= MD_CK0;
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+
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+ r8a7740_clock_init(md_ck);
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+ shmobile_timer.init();
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+}
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+
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+struct sys_timer bonito_timer = {
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+ .init = bonito_timer_init,
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+};
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+
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+MACHINE_START(BONITO, "bonito")
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+ .map_io = bonito_map_io,
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+ .init_irq = r8a7740_init_irq,
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+ .handle_irq = shmobile_handle_irq_intc,
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+ .init_machine = bonito_init,
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+ .timer = &bonito_timer,
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+MACHINE_END
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Kuninori Morimoto