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@@ -53,6 +53,7 @@
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#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
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#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
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#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
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+#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
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#define SSB_CHIPCO_CORECTL 0x0008
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#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
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#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
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@@ -385,6 +386,7 @@
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/** Chip specific Chip-Status register contents. */
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+#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
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#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
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#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
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#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
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@@ -398,6 +400,18 @@
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#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
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#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
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+/** Macros to determine SPROM presence based on Chip-Status register. */
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+#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
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+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
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+ SSB_CHIPCO_CHST_4325_OTP_SEL)
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+#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
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+ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
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+#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
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+ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
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+ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
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+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
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+ SSB_CHIPCO_CHST_4325_OTP_SEL))
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+
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/** Clockcontrol masks and values **/
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@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
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struct ssb_chipcommon {
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struct ssb_device *dev;
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u32 capabilities;
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+ u32 status;
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/* Fast Powerup Delay constant */
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u16 fast_pwrup_delay;
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struct ssb_chipcommon_pmu pmu;
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