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@@ -491,8 +491,7 @@ ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
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sii->pub.ccrev = cc->id.rev;
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/* get chipcommon chipstatus */
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- if (ai_get_ccrev(&sii->pub) >= 11)
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- sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
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+ sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
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/* get chipcommon capabilites */
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sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities));
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@@ -721,21 +720,7 @@ uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val)
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/* return the slow clock source - LPO, XTAL, or PCI */
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static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
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{
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- struct si_info *sii;
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- u32 val;
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-
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- sii = (struct si_info *)sih;
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- if (ai_get_ccrev(&sii->pub) < 6) {
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- pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT,
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- &val);
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- if (val & PCI_CFG_GPIO_SCS)
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- return SCC_SS_PCI;
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- return SCC_SS_XTAL;
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- } else if (ai_get_ccrev(&sii->pub) < 10) {
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- return bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
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- SCC_SS_MASK;
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- } else /* Insta-clock */
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- return SCC_SS_XTAL;
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+ return SCC_SS_XTAL;
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}
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/*
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@@ -745,36 +730,12 @@ static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
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static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq,
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struct bcma_device *cc)
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{
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- u32 slowclk;
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uint div;
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- slowclk = ai_slowclk_src(sih, cc);
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- if (ai_get_ccrev(sih) < 6) {
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- if (slowclk == SCC_SS_PCI)
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- return max_freq ? (PCIMAXFREQ / 64)
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- : (PCIMINFREQ / 64);
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- else
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- return max_freq ? (XTALMAXFREQ / 32)
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- : (XTALMINFREQ / 32);
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- } else if (ai_get_ccrev(sih) < 10) {
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- div = 4 *
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- (((bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
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- SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
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- if (slowclk == SCC_SS_LPO)
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- return max_freq ? LPOMAXFREQ : LPOMINFREQ;
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- else if (slowclk == SCC_SS_XTAL)
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- return max_freq ? (XTALMAXFREQ / div)
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- : (XTALMINFREQ / div);
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- else if (slowclk == SCC_SS_PCI)
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- return max_freq ? (PCIMAXFREQ / div)
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- : (PCIMINFREQ / div);
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- } else {
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- /* Chipc rev 10 is InstaClock */
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- div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
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- div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
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- return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
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- }
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- return 0;
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+ /* Chipc rev 10 is InstaClock */
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+ div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
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+ div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
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+ return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
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}
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static void
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@@ -797,8 +758,7 @@ ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc)
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/* Starting with 4318 it is ILP that is used for the delays */
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slowmaxfreq =
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- ai_slowclk_freq(sih,
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- (ai_get_ccrev(sih) >= 10) ? false : true, cc);
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+ ai_slowclk_freq(sih, false, cc);
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pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
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fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
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@@ -820,9 +780,8 @@ void ai_clkctl_init(struct si_pub *sih)
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return;
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/* set all Instaclk chip ILP to 1 MHz */
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- if (ai_get_ccrev(sih) >= 10)
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- bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
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- (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
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+ bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
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+ (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
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ai_clkctl_setdelay(sih, cc);
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}
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@@ -926,31 +885,11 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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struct bcma_device *cc;
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u32 scc;
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- /* chipcommon cores prior to rev6 don't support dynamic clock control */
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- if (ai_get_ccrev(&sii->pub) < 6)
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- return false;
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-
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cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
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- if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) &&
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- (ai_get_ccrev(&sii->pub) < 20))
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- return mode == CLK_FAST;
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-
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switch (mode) {
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case CLK_FAST: /* FORCEHT, fast (pll) clock */
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- if (ai_get_ccrev(&sii->pub) < 10) {
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- /*
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- * don't forget to force xtal back
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- * on before we clear SCC_DYN_XTAL..
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- */
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- ai_clkctl_xtal(&sii->pub, XTAL, ON);
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- bcma_maskset32(cc, CHIPCREGOFFS(slow_clk_ctl),
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- (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
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- } else if (ai_get_ccrev(&sii->pub) < 20) {
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- bcma_set32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_HR);
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- } else {
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- bcma_set32(cc, CHIPCREGOFFS(clk_ctl_st), CCS_FORCEHT);
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- }
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+ bcma_set32(cc, CHIPCREGOFFS(clk_ctl_st), CCS_FORCEHT);
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/* wait for the PLL */
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if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
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@@ -963,25 +902,7 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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break;
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case CLK_DYNAMIC: /* enable dynamic clock control */
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- if (ai_get_ccrev(&sii->pub) < 10) {
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- scc = bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl));
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- scc &= ~(SCC_FS | SCC_IP | SCC_XC);
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- if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
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- scc |= SCC_XC;
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- bcma_write32(cc, CHIPCREGOFFS(slow_clk_ctl), scc);
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-
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- /*
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- * for dynamic control, we have to
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- * release our xtal_pu "force on"
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- */
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- if (scc & SCC_XC)
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- ai_clkctl_xtal(&sii->pub, XTAL, OFF);
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- } else if (ai_get_ccrev(&sii->pub) < 20) {
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- /* Instaclock */
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- bcma_mask32(cc, CHIPCREGOFFS(system_clk_ctl), ~SYCC_HR);
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- } else {
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- bcma_mask32(cc, CHIPCREGOFFS(clk_ctl_st), ~CCS_FORCEHT);
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- }
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+ bcma_mask32(cc, CHIPCREGOFFS(clk_ctl_st), ~CCS_FORCEHT);
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break;
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default:
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@@ -1005,10 +926,6 @@ bool ai_clkctl_cc(struct si_pub *sih, uint mode)
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sii = (struct si_info *)sih;
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- /* chipcommon cores prior to rev6 don't support dynamic clock control */
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- if (ai_get_ccrev(sih) < 6)
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- return false;
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-
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if (PCI_FORCEHT(sih))
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return mode == CLK_FAST;
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