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@@ -328,6 +328,28 @@
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#define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
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#define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
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#define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2))
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#define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2))
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+
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+/*******************************
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+ * Memory Controller *
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+ *******************************/
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+
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+/* Registers */
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+#define NETX_MEMCR_REG(ofs) __io(NETX_VA_MEMCR + (ofs))
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+#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
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+#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40)
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+#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44)
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+#define NETX_MEMCR_SDRAM_MODE NETX_MEMCR_REG(0x48)
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+#define NETX_MEMCR_SDRAM_EXT_MODE NETX_MEMCR_REG(0x4c)
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+#define NETX_MEMCR_PRIO_TIMESLOT_CTRL NETX_MEMCR_REG(0x80)
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+#define NETX_MEMCR_PRIO_ACCESS_CTRL NETX_MEMCR_REG(0x84)
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+
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+/* Bits */
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+#define NETX_MEMCR_SRAM_CTRL_WIDTHEXTMEM(x) (((x) & 0x3) << 24)
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+#define NETX_MEMCR_SRAM_CTRL_WSPOSTPAUSEEXTMEM(x) (((x) & 0x3) << 16)
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+#define NETX_MEMCR_SRAM_CTRL_WSPREPASEEXTMEM(x) (((x) & 0x3) << 8)
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+#define NETX_MEMCR_SRAM_CTRL_WSEXTMEM(x) (((x) & 0x1f) << 0)
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+
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+
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/*******************************
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/*******************************
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* Dual Port Memory *
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* Dual Port Memory *
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*******************************/
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*******************************/
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