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@@ -1,6 +1,21 @@
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#ifndef MFD_TMIO_H
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#define MFD_TMIO_H
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+#define tmio_ioread8(addr) readb(addr)
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+#define tmio_ioread16(addr) readw(addr)
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+#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
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+#define tmio_ioread32(addr) \
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+ (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
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+
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+#define tmio_iowrite8(val, addr) writeb((val), (addr))
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+#define tmio_iowrite16(val, addr) writew((val), (addr))
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+#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
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+#define tmio_iowrite32(val, addr) \
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+ do { \
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+ writew((val), (addr)); \
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+ writew((val) >> 16, (addr) + 2); \
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+ } while (0)
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+
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/*
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* data for the NAND controller
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*/
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@@ -10,8 +25,4 @@ struct tmio_nand_data {
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unsigned int num_partitions;
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};
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-#define TMIO_NAND_CONFIG "tmio-nand-config"
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-#define TMIO_NAND_CONTROL "tmio-nand-control"
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-#define TMIO_NAND_IRQ "tmio-nand"
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-
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#endif
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