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@@ -30,9 +30,13 @@
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* Shared functions for accessing and configuring the adapter
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*/
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+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+
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#include "ixgb_hw.h"
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#include "ixgb_ids.h"
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+#include <linux/etherdevice.h>
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+
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/* Local function prototypes */
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static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
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@@ -120,13 +124,13 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
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u32 ctrl_reg;
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u32 icr_reg;
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- DEBUGFUNC("ixgb_adapter_stop");
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+ ENTER();
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/* If we are stopped or resetting exit gracefully and wait to be
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* started again before accessing the hardware.
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*/
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if (hw->adapter_stopped) {
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- DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
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+ pr_debug("Exiting because the adapter is already stopped!!!\n");
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return false;
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}
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@@ -136,7 +140,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
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hw->adapter_stopped = true;
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/* Clear interrupt mask to stop board from generating interrupts */
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- DEBUGOUT("Masking off all interrupts\n");
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+ pr_debug("Masking off all interrupts\n");
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IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
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/* Disable the Transmit and Receive units. Then delay to allow
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@@ -152,12 +156,12 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
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* the current PCI configuration. The global reset bit is self-
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* clearing, and should clear within a microsecond.
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*/
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- DEBUGOUT("Issuing a global reset to MAC\n");
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+ pr_debug("Issuing a global reset to MAC\n");
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ctrl_reg = ixgb_mac_reset(hw);
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/* Clear interrupt mask to stop board from generating interrupts */
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- DEBUGOUT("Masking off all interrupts\n");
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+ pr_debug("Masking off all interrupts\n");
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IXGB_WRITE_REG(hw, IMC, 0xffffffff);
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/* Clear any pending interrupt events. */
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@@ -183,7 +187,7 @@ ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
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u16 vendor_name[5];
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ixgb_xpak_vendor xpak_vendor;
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- DEBUGFUNC("ixgb_identify_xpak_vendor");
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+ ENTER();
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/* Read the first few bytes of the vendor string from the XPAK NVR
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* registers. These are standard XENPAK/XPAK registers, so all XPAK
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@@ -222,12 +226,12 @@ ixgb_identify_phy(struct ixgb_hw *hw)
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ixgb_phy_type phy_type;
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ixgb_xpak_vendor xpak_vendor;
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- DEBUGFUNC("ixgb_identify_phy");
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+ ENTER();
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/* Infer the transceiver/phy type from the device id */
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switch (hw->device_id) {
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case IXGB_DEVICE_ID_82597EX:
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- DEBUGOUT("Identified TXN17401 optics\n");
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+ pr_debug("Identified TXN17401 optics\n");
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phy_type = ixgb_phy_type_txn17401;
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break;
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@@ -237,30 +241,30 @@ ixgb_identify_phy(struct ixgb_hw *hw)
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* type of optics. */
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xpak_vendor = ixgb_identify_xpak_vendor(hw);
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if (xpak_vendor == ixgb_xpak_vendor_intel) {
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- DEBUGOUT("Identified TXN17201 optics\n");
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+ pr_debug("Identified TXN17201 optics\n");
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phy_type = ixgb_phy_type_txn17201;
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} else {
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- DEBUGOUT("Identified G6005 optics\n");
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+ pr_debug("Identified G6005 optics\n");
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phy_type = ixgb_phy_type_g6005;
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}
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break;
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case IXGB_DEVICE_ID_82597EX_LR:
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- DEBUGOUT("Identified G6104 optics\n");
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+ pr_debug("Identified G6104 optics\n");
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phy_type = ixgb_phy_type_g6104;
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break;
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case IXGB_DEVICE_ID_82597EX_CX4:
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- DEBUGOUT("Identified CX4\n");
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+ pr_debug("Identified CX4\n");
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xpak_vendor = ixgb_identify_xpak_vendor(hw);
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if (xpak_vendor == ixgb_xpak_vendor_intel) {
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- DEBUGOUT("Identified TXN17201 optics\n");
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+ pr_debug("Identified TXN17201 optics\n");
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phy_type = ixgb_phy_type_txn17201;
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} else {
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- DEBUGOUT("Identified G6005 optics\n");
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+ pr_debug("Identified G6005 optics\n");
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phy_type = ixgb_phy_type_g6005;
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}
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break;
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default:
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- DEBUGOUT("Unknown physical layer module\n");
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+ pr_debug("Unknown physical layer module\n");
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phy_type = ixgb_phy_type_unknown;
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break;
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}
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@@ -296,18 +300,18 @@ ixgb_init_hw(struct ixgb_hw *hw)
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u32 ctrl_reg;
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bool status;
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- DEBUGFUNC("ixgb_init_hw");
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+ ENTER();
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/* Issue a global reset to the MAC. This will reset the chip's
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* transmit, receive, DMA, and link units. It will not effect
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* the current PCI configuration. The global reset bit is self-
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* clearing, and should clear within a microsecond.
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*/
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- DEBUGOUT("Issuing a global reset to MAC\n");
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+ pr_debug("Issuing a global reset to MAC\n");
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ctrl_reg = ixgb_mac_reset(hw);
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- DEBUGOUT("Issuing an EE reset to MAC\n");
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+ pr_debug("Issuing an EE reset to MAC\n");
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#ifdef HP_ZX1
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/* Workaround for 82597EX reset errata */
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IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
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@@ -335,7 +339,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
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* If it is not valid, we fail hardware init.
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*/
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if (!mac_addr_valid(hw->curr_mac_addr)) {
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- DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
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+ pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
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return(false);
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}
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@@ -346,7 +350,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
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ixgb_get_bus_info(hw);
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/* Zero out the Multicast HASH table */
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- DEBUGOUT("Zeroing the MTA\n");
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+ pr_debug("Zeroing the MTA\n");
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for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
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IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
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@@ -379,7 +383,7 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
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{
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u32 i;
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- DEBUGFUNC("ixgb_init_rx_addrs");
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+ ENTER();
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/*
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* If the current mac address is valid, assume it is a software override
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@@ -391,28 +395,19 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
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/* Get the MAC address from the eeprom for later reference */
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ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
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- DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
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- hw->curr_mac_addr[0],
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- hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
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- DEBUGOUT3("%.2X %.2X %.2X\n",
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- hw->curr_mac_addr[3],
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- hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
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+ pr_debug("Keeping Permanent MAC Addr = %pM\n",
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+ hw->curr_mac_addr);
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} else {
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/* Setup the receive address. */
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- DEBUGOUT("Overriding MAC Address in RAR[0]\n");
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- DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
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- hw->curr_mac_addr[0],
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- hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
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- DEBUGOUT3("%.2X %.2X %.2X\n",
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- hw->curr_mac_addr[3],
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- hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
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+ pr_debug("Overriding MAC Address in RAR[0]\n");
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+ pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
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ixgb_rar_set(hw, hw->curr_mac_addr, 0);
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}
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/* Zero out the other 15 receive addresses. */
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- DEBUGOUT("Clearing RAR[1-15]\n");
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+ pr_debug("Clearing RAR[1-15]\n");
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for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
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/* Write high reg first to disable the AV bit first */
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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@@ -444,64 +439,50 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
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u32 hash_value;
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u32 i;
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u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
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+ u8 *mca;
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- DEBUGFUNC("ixgb_mc_addr_list_update");
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+ ENTER();
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/* Set the new number of MC addresses that we are being requested to use. */
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hw->num_mc_addrs = mc_addr_count;
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/* Clear RAR[1-15] */
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- DEBUGOUT(" Clearing RAR[1-15]\n");
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+ pr_debug("Clearing RAR[1-15]\n");
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for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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}
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/* Clear the MTA */
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- DEBUGOUT(" Clearing MTA\n");
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+ pr_debug("Clearing MTA\n");
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for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
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IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
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/* Add the new addresses */
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+ mca = mc_addr_list;
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for (i = 0; i < mc_addr_count; i++) {
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- DEBUGOUT(" Adding the multicast addresses:\n");
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- DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
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- mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
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- mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
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- 1],
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- mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
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- 2],
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- mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
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- 3],
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- mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
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- 4],
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- mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
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- 5]);
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+ pr_debug("Adding the multicast addresses:\n");
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+ pr_debug("MC Addr #%d = %pM\n", i, mca);
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/* Place this multicast address in the RAR if there is room, *
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* else put it in the MTA
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*/
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if (rar_used_count < IXGB_RAR_ENTRIES) {
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- ixgb_rar_set(hw,
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- mc_addr_list +
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- (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
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- rar_used_count);
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- DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
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+ ixgb_rar_set(hw, mca, rar_used_count);
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+ pr_debug("Added a multicast address to RAR[%d]\n", i);
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rar_used_count++;
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} else {
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- hash_value = ixgb_hash_mc_addr(hw,
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- mc_addr_list +
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- (i *
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- (IXGB_ETH_LENGTH_OF_ADDRESS
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- + pad)));
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+ hash_value = ixgb_hash_mc_addr(hw, mca);
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- DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
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+ pr_debug("Hash value = 0x%03X\n", hash_value);
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ixgb_mta_set(hw, hash_value);
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}
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+
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+ mca += IXGB_ETH_LENGTH_OF_ADDRESS + pad;
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}
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- DEBUGOUT("MC Update Complete\n");
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+ pr_debug("MC Update Complete\n");
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return;
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}
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@@ -520,7 +501,7 @@ ixgb_hash_mc_addr(struct ixgb_hw *hw,
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{
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u32 hash_value = 0;
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- DEBUGFUNC("ixgb_hash_mc_addr");
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+ ENTER();
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/* The portion of the address that is used for the hash table is
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* determined by the mc_filter_type setting.
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@@ -547,7 +528,7 @@ ixgb_hash_mc_addr(struct ixgb_hw *hw,
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break;
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default:
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/* Invalid mc_filter_type, what should we do? */
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- DEBUGOUT("MC filter type param set incorrectly\n");
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+ pr_debug("MC filter type param set incorrectly\n");
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ASSERT(0);
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break;
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}
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@@ -603,7 +584,7 @@ ixgb_rar_set(struct ixgb_hw *hw,
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{
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u32 rar_low, rar_high;
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- DEBUGFUNC("ixgb_rar_set");
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+ ENTER();
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/* HW expects these in little endian so we reverse the byte order
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* from network order (big endian) to little endian
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@@ -666,7 +647,7 @@ ixgb_setup_fc(struct ixgb_hw *hw)
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u32 pap_reg = 0; /* by default, assume no pause time */
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bool status = true;
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- DEBUGFUNC("ixgb_setup_fc");
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+ ENTER();
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/* Get the current control reg 0 settings */
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ctrl_reg = IXGB_READ_REG(hw, CTRL0);
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@@ -710,7 +691,7 @@ ixgb_setup_fc(struct ixgb_hw *hw)
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break;
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default:
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/* We should never get here. The value should be 0-3. */
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- DEBUGOUT("Flow control param set incorrectly\n");
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+ pr_debug("Flow control param set incorrectly\n");
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ASSERT(0);
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break;
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}
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@@ -940,7 +921,7 @@ ixgb_check_for_link(struct ixgb_hw *hw)
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u32 status_reg;
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u32 xpcss_reg;
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- DEBUGFUNC("ixgb_check_for_link");
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+ ENTER();
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xpcss_reg = IXGB_READ_REG(hw, XPCSS);
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status_reg = IXGB_READ_REG(hw, STATUS);
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@@ -950,7 +931,7 @@ ixgb_check_for_link(struct ixgb_hw *hw)
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hw->link_up = true;
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} else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
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(status_reg & IXGB_STATUS_LU)) {
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- DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
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+ pr_debug("XPCSS Not Aligned while Status:LU is set\n");
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hw->link_up = ixgb_link_reset(hw);
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} else {
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/*
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@@ -981,8 +962,7 @@ bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
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newRFC = IXGB_READ_REG(hw, RFC);
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if ((hw->lastLFC + 250 < newLFC)
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|| (hw->lastRFC + 250 < newRFC)) {
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- DEBUGOUT
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- ("BAD LINK! too many LFC/RFC since last check\n");
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+ pr_debug("BAD LINK! too many LFC/RFC since last check\n");
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bad_link_returncode = true;
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}
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hw->lastLFC = newLFC;
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@@ -1002,11 +982,11 @@ ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
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{
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volatile u32 temp_reg;
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- DEBUGFUNC("ixgb_clear_hw_cntrs");
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+ ENTER();
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/* if we are stopped or resetting exit gracefully */
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if (hw->adapter_stopped) {
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- DEBUGOUT("Exiting because the adapter is stopped!!!\n");
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+ pr_debug("Exiting because the adapter is stopped!!!\n");
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return;
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}
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@@ -1156,26 +1136,21 @@ static bool
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mac_addr_valid(u8 *mac_addr)
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{
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bool is_valid = true;
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- DEBUGFUNC("mac_addr_valid");
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+ ENTER();
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/* Make sure it is not a multicast address */
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- if (IS_MULTICAST(mac_addr)) {
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- DEBUGOUT("MAC address is multicast\n");
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+ if (is_multicast_ether_addr(mac_addr)) {
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+ pr_debug("MAC address is multicast\n");
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is_valid = false;
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}
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/* Not a broadcast address */
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- else if (IS_BROADCAST(mac_addr)) {
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- DEBUGOUT("MAC address is broadcast\n");
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+ else if (is_broadcast_ether_addr(mac_addr)) {
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+ pr_debug("MAC address is broadcast\n");
|
|
|
is_valid = false;
|
|
|
}
|
|
|
/* Reject the zero address */
|
|
|
- else if (mac_addr[0] == 0 &&
|
|
|
- mac_addr[1] == 0 &&
|
|
|
- mac_addr[2] == 0 &&
|
|
|
- mac_addr[3] == 0 &&
|
|
|
- mac_addr[4] == 0 &&
|
|
|
- mac_addr[5] == 0) {
|
|
|
- DEBUGOUT("MAC address is all zeros\n");
|
|
|
+ else if (is_zero_ether_addr(mac_addr)) {
|
|
|
+ pr_debug("MAC address is all zeros\n");
|
|
|
is_valid = false;
|
|
|
}
|
|
|
return (is_valid);
|