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@@ -118,7 +118,7 @@ enum {
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PIIX_80C_SEC = (1 << 7) | (1 << 6),
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/* controller IDs */
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- piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
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+ piix_pata_33 = 0, /* PIIX4 at 33Mhz */
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ich_pata_33 = 1, /* ICH up to UDMA 33 only */
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ich_pata_66 = 2, /* ICH up to 66 Mhz */
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ich_pata_100 = 3, /* ICH up to UDMA 100 */
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@@ -128,6 +128,7 @@ enum {
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ich6_sata_ahci = 7,
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ich6m_sata_ahci = 8,
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ich8_sata_ahci = 9,
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+ piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
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/* constants for mapping table */
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P0 = 0, /* port 0 */
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@@ -165,6 +166,8 @@ static unsigned int in_module_init = 1;
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static const struct pci_device_id piix_pci_tbl[] = {
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#ifdef ATA_ENABLE_PATA
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+ /* Intel PIIX3 for the 430HX etc */
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+ { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
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/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
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/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
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{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
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@@ -441,7 +444,7 @@ static const struct piix_map_db *piix_map_db_table[] = {
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};
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static struct ata_port_info piix_port_info[] = {
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- /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
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+ /* piix_pata_33: 0: PIIX4 at 33MHz */
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{
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.sht = &piix_sht,
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.flags = PIIX_PATA_FLAGS,
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@@ -543,6 +546,14 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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},
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+ /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
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+ {
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+ .sht = &piix_sht,
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+ .flags = PIIX_PATA_FLAGS,
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+ .pio_mask = 0x1f, /* pio0-4 */
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+ .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
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+ .port_ops = &piix_pata_ops,
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+ },
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};
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static struct pci_bits piix_enable_bits[] = {
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@@ -787,7 +798,8 @@ static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, i
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{ 2, 3 }, };
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pci_read_config_word(dev, master_port, &master_data);
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- pci_read_config_byte(dev, 0x48, &udma_enable);
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+ if (ap->udma_mask)
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+ pci_read_config_byte(dev, 0x48, &udma_enable);
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if (speed >= XFER_UDMA_0) {
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unsigned int udma = adev->dma_mode - XFER_UDMA_0;
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