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@@ -1,5 +1,158 @@
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+#ifndef _ASM_X86_TLBFLUSH_H
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+#define _ASM_X86_TLBFLUSH_H
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+
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+#include <linux/mm.h>
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+#include <linux/sched.h>
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+
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+#include <asm/processor.h>
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+#include <asm/system.h>
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+
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+#ifdef CONFIG_PARAVIRT
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+#include <asm/paravirt.h>
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+#else
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+#define __flush_tlb() __native_flush_tlb()
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+#define __flush_tlb_global() __native_flush_tlb_global()
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+#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
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+#endif
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+
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+static inline void __native_flush_tlb(void)
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+{
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+ write_cr3(read_cr3());
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+}
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+
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+static inline void __native_flush_tlb_global(void)
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+{
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+ unsigned long cr4 = read_cr4();
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+
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+ /* clear PGE */
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+ write_cr4(cr4 & ~X86_CR4_PGE);
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+ /* write old PGE again and flush TLBs */
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+ write_cr4(cr4);
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+}
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+
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+static inline void __native_flush_tlb_single(unsigned long addr)
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+{
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+ __asm__ __volatile__("invlpg (%0)" ::"r" (addr) : "memory");
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+}
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+
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+static inline void __flush_tlb_all(void)
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+{
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+ if (cpu_has_pge)
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+ __flush_tlb_global();
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+ else
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+ __flush_tlb();
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+}
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+
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+static inline void __flush_tlb_one(unsigned long addr)
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+{
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+ if (cpu_has_invlpg)
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+ __flush_tlb_single(addr);
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+ else
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+ __flush_tlb();
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+}
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+
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#ifdef CONFIG_X86_32
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-# include "tlbflush_32.h"
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+# define TLB_FLUSH_ALL 0xffffffff
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#else
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-# include "tlbflush_64.h"
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+# define TLB_FLUSH_ALL -1ULL
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+#endif
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+
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+/*
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+ * TLB flushing:
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+ *
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+ * - flush_tlb() flushes the current mm struct TLBs
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+ * - flush_tlb_all() flushes all processes TLBs
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+ * - flush_tlb_mm(mm) flushes the specified mm context TLB's
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+ * - flush_tlb_page(vma, vmaddr) flushes one page
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+ * - flush_tlb_range(vma, start, end) flushes a range of pages
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+ * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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+ * - flush_tlb_others(cpumask, mm, va) flushes TLBs on other cpus
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+ *
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+ * ..but the i386 has somewhat limited tlb flushing capabilities,
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+ * and page-granular flushes are available only on i486 and up.
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+ *
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+ * x86-64 can only flush individual pages or full VMs. For a range flush
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+ * we always do the full VM. Might be worth trying if for a small
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+ * range a few INVLPGs in a row are a win.
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+ */
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+
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+#ifndef CONFIG_SMP
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+
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+#define flush_tlb() __flush_tlb()
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+#define flush_tlb_all() __flush_tlb_all()
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+#define local_flush_tlb() __flush_tlb()
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+
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+static inline void flush_tlb_mm(struct mm_struct *mm)
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+{
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+ if (mm == current->active_mm)
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+ __flush_tlb();
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+}
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+
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+static inline void flush_tlb_page(struct vm_area_struct *vma,
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+ unsigned long addr)
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+{
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+ if (vma->vm_mm == current->active_mm)
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+ __flush_tlb_one(addr);
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+}
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+
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+static inline void flush_tlb_range(struct vm_area_struct *vma,
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+ unsigned long start, unsigned long end)
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+{
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+ if (vma->vm_mm == current->active_mm)
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+ __flush_tlb();
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+}
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+
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+static inline void native_flush_tlb_others(const cpumask_t *cpumask,
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+ struct mm_struct *mm,
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+ unsigned long va)
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+{
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+}
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+
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+#else /* SMP */
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+
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+#include <asm/smp.h>
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+
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+#define local_flush_tlb() __flush_tlb()
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+
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+extern void flush_tlb_all(void);
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+extern void flush_tlb_current_task(void);
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+extern void flush_tlb_mm(struct mm_struct *);
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+extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
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+
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+#define flush_tlb() flush_tlb_current_task()
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+
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+static inline void flush_tlb_range(struct vm_area_struct *vma,
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+ unsigned long start, unsigned long end)
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+{
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+ flush_tlb_mm(vma->vm_mm);
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+}
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+
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+void native_flush_tlb_others(const cpumask_t *cpumask, struct mm_struct *mm,
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+ unsigned long va);
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+
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+#define TLBSTATE_OK 1
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+#define TLBSTATE_LAZY 2
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+
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+#ifdef CONFIG_X86_32
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+struct tlb_state
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+{
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+ struct mm_struct *active_mm;
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+ int state;
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+ char __cacheline_padding[L1_CACHE_BYTES-8];
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+};
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+DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate);
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+#endif
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+
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+#endif /* SMP */
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+
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+#ifndef CONFIG_PARAVIRT
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+#define flush_tlb_others(mask, mm, va) native_flush_tlb_others(&mask, mm, va)
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#endif
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+
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+static inline void flush_tlb_kernel_range(unsigned long start,
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+ unsigned long end)
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+{
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+ flush_tlb_all();
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+}
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+
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+#endif /* _ASM_X86_TLBFLUSH_H */
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Thomas Gleixner