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@@ -346,29 +346,6 @@ void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val
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writel(value, &io_apic->data);
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}
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-static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
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-{
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- struct irq_pin_list *entry;
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- unsigned long flags;
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-
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- raw_spin_lock_irqsave(&ioapic_lock, flags);
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- for_each_irq_pin(entry, cfg->irq_2_pin) {
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- unsigned int reg;
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- int pin;
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-
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- pin = entry->pin;
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- reg = io_apic_read(entry->apic, 0x10 + pin*2);
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- /* Is the remote IRR bit set? */
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- if (reg & IO_APIC_REDIR_REMOTE_IRR) {
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- raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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- return true;
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- }
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- }
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- raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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-
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- return false;
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-}
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-
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union entry_union {
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struct { u32 w1, w2; };
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struct IO_APIC_route_entry entry;
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@@ -2519,6 +2496,29 @@ static void ack_apic_edge(struct irq_data *data)
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atomic_t irq_mis_count;
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#ifdef CONFIG_GENERIC_PENDING_IRQ
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+static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
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+{
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+ struct irq_pin_list *entry;
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+ unsigned long flags;
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+
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+ raw_spin_lock_irqsave(&ioapic_lock, flags);
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+ for_each_irq_pin(entry, cfg->irq_2_pin) {
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+ unsigned int reg;
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+ int pin;
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+
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+ pin = entry->pin;
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+ reg = io_apic_read(entry->apic, 0x10 + pin*2);
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+ /* Is the remote IRR bit set? */
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+ if (reg & IO_APIC_REDIR_REMOTE_IRR) {
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+ raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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+ return true;
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+ }
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+ }
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+ raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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+
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+ return false;
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+}
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+
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static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
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{
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/* If we are moving the irq we need to mask it */
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