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@@ -34,7 +34,7 @@ struct wd_ops {
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u64 checkbit;
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};
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-static struct wd_ops *wd_ops;
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+static const struct wd_ops *wd_ops;
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/* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
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* offset from MSR_P4_BSU_ESCR0. It will be the max for all platforms (for now)
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@@ -317,7 +317,7 @@ static void single_msr_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
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write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
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}
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-static struct wd_ops k7_wd_ops = {
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+static const struct wd_ops k7_wd_ops = {
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_k7_watchdog,
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@@ -380,7 +380,7 @@ static void p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
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write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz);
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}
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-static struct wd_ops p6_wd_ops = {
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+static const struct wd_ops p6_wd_ops = {
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_p6_watchdog,
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@@ -532,7 +532,7 @@ static void p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
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write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
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}
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-static struct wd_ops p4_wd_ops = {
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+static const struct wd_ops p4_wd_ops = {
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.reserve = p4_reserve,
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.unreserve = p4_unreserve,
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.setup = setup_p4_watchdog,
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@@ -550,6 +550,8 @@ static struct wd_ops p4_wd_ops = {
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#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
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#define ARCH_PERFMON_NMI_EVENT_UMASK ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
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+static struct wd_ops intel_arch_wd_ops;
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+
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static int setup_intel_arch_watchdog(unsigned nmi_hz)
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{
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unsigned int ebx;
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@@ -591,11 +593,11 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
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wd->perfctr_msr = perfctr_msr;
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wd->evntsel_msr = evntsel_msr;
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wd->cccr_msr = 0; //unused
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- wd_ops->checkbit = 1ULL << (eax.split.bit_width - 1);
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+ intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
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return 1;
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}
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-static struct wd_ops intel_arch_wd_ops = {
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+static struct wd_ops intel_arch_wd_ops __read_mostly = {
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.reserve = single_msr_reserve,
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.unreserve = single_msr_unreserve,
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.setup = setup_intel_arch_watchdog,
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