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@@ -35,9 +35,9 @@
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* Timer Register Offset Definitions of Timer 1, Increment base address by 4
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* and use same offsets for Timer 2
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*/
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-#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
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-#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
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-#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
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+#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
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+#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
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+#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
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#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
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#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
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#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
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