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@@ -33,7 +33,6 @@
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/hardirq.h>
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-#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sizes.h>
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@@ -47,21 +46,6 @@
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/* DISPC */
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#define DISPC_SZ_REGS SZ_4K
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-#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
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- DISPC_IRQ_OCP_ERR | \
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- DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
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- DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
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- DISPC_IRQ_SYNC_LOST | \
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- DISPC_IRQ_SYNC_LOST_DIGIT)
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-
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-#define DISPC_MAX_NR_ISRS 8
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-
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-struct omap_dispc_isr_data {
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- omap_dispc_isr_t isr;
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- void *arg;
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- u32 mask;
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-};
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-
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enum omap_burst_size {
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BURST_SIZE_X2 = 0,
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BURST_SIZE_X4 = 1,
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@@ -74,12 +58,6 @@ enum omap_burst_size {
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#define REG_FLD_MOD(idx, val, start, end) \
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dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
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-struct dispc_irq_stats {
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- unsigned long last_reset;
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- unsigned irq_count;
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- unsigned irqs[32];
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-};
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-
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struct dispc_features {
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u8 sw_start;
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u8 fp_start;
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@@ -124,21 +102,10 @@ static struct {
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/* maps which plane is using a fifo. fifo-id -> plane-id */
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int fifo_assignment[DISPC_MAX_NR_FIFOS];
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- spinlock_t irq_lock;
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- u32 irq_error_mask;
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- struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
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- u32 error_irqs;
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- struct work_struct error_work;
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-
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bool ctx_valid;
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u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
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const struct dispc_features *feat;
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-
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-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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- spinlock_t irq_stats_lock;
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- struct dispc_irq_stats irq_stats;
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-#endif
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} dispc;
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enum omap_color_component {
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@@ -249,7 +216,6 @@ struct color_conv_coef {
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int full_range;
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};
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-static void _omap_dispc_set_irqs(void);
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static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
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static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
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@@ -528,6 +494,7 @@ int dispc_runtime_get(void)
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WARN_ON(r < 0);
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return r < 0 ? r : 0;
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}
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+EXPORT_SYMBOL(dispc_runtime_get);
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void dispc_runtime_put(void)
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{
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@@ -538,11 +505,13 @@ void dispc_runtime_put(void)
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r = pm_runtime_put_sync(&dispc.pdev->dev);
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WARN_ON(r < 0 && r != -ENOSYS);
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}
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+EXPORT_SYMBOL(dispc_runtime_put);
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u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
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{
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return mgr_desc[channel].vsync_irq;
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}
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+EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
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u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
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{
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@@ -551,11 +520,13 @@ u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
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return mgr_desc[channel].framedone_irq;
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}
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+EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
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u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
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{
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return mgr_desc[channel].sync_lost_irq;
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}
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+EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
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u32 dispc_wb_get_framedone_irq(void)
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{
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@@ -566,6 +537,7 @@ bool dispc_mgr_go_busy(enum omap_channel channel)
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{
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return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
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}
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+EXPORT_SYMBOL(dispc_mgr_go_busy);
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void dispc_mgr_go(enum omap_channel channel)
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{
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@@ -576,6 +548,7 @@ void dispc_mgr_go(enum omap_channel channel)
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mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
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}
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+EXPORT_SYMBOL(dispc_mgr_go);
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bool dispc_wb_go_busy(void)
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{
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@@ -979,6 +952,7 @@ void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
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}
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dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
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}
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+EXPORT_SYMBOL(dispc_ovl_set_channel_out);
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static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
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{
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@@ -2354,6 +2328,47 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
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return 0;
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}
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+int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
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+ const struct omap_overlay_info *oi,
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+ const struct omap_video_timings *timings,
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+ int *x_predecim, int *y_predecim)
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+{
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+ enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
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+ bool five_taps = true;
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+ bool fieldmode = 0;
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+ u16 in_height = oi->height;
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+ u16 in_width = oi->width;
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+ bool ilace = timings->interlace;
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+ u16 out_width, out_height;
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+ int pos_x = oi->pos_x;
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+ unsigned long pclk = dispc_mgr_pclk_rate(channel);
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+ unsigned long lclk = dispc_mgr_lclk_rate(channel);
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+
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+ out_width = oi->out_width == 0 ? oi->width : oi->out_width;
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+ out_height = oi->out_height == 0 ? oi->height : oi->out_height;
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+
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+ if (ilace && oi->height == out_height)
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+ fieldmode = 1;
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+
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+ if (ilace) {
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+ if (fieldmode)
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+ in_height /= 2;
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+ out_height /= 2;
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+
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+ DSSDBG("adjusting for ilace: height %d, out_height %d\n",
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+ in_height, out_height);
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+ }
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+
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+ if (!dss_feat_color_mode_supported(plane, oi->color_mode))
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+ return -EINVAL;
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+
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+ return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
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+ in_height, out_width, out_height, oi->color_mode,
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+ &five_taps, x_predecim, y_predecim, pos_x,
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+ oi->rotation_type, false);
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+}
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+EXPORT_SYMBOL(dispc_ovl_check);
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+
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static int dispc_ovl_setup_common(enum omap_plane plane,
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enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
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u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
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@@ -2533,6 +2548,7 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
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return r;
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}
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+EXPORT_SYMBOL(dispc_ovl_setup);
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int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
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bool mem_to_mem, const struct omap_video_timings *mgr_timings)
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@@ -2593,17 +2609,13 @@ int dispc_ovl_enable(enum omap_plane plane, bool enable)
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return 0;
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}
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+EXPORT_SYMBOL(dispc_ovl_enable);
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bool dispc_ovl_enabled(enum omap_plane plane)
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{
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return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
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}
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-
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-static void dispc_mgr_disable_isr(void *data, u32 mask)
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-{
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- struct completion *compl = data;
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- complete(compl);
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-}
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+EXPORT_SYMBOL(dispc_ovl_enabled);
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void dispc_mgr_enable(enum omap_channel channel, bool enable)
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{
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@@ -2611,180 +2623,13 @@ void dispc_mgr_enable(enum omap_channel channel, bool enable)
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/* flush posted write */
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mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
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}
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+EXPORT_SYMBOL(dispc_mgr_enable);
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bool dispc_mgr_is_enabled(enum omap_channel channel)
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{
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return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
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}
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-
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-static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
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-{
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- dispc_mgr_enable(channel, true);
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-}
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-
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-static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
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-{
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- DECLARE_COMPLETION_ONSTACK(framedone_compl);
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- int r;
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- u32 irq;
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-
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- if (dispc_mgr_is_enabled(channel) == false)
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- return;
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-
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- /*
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- * When we disable LCD output, we need to wait for FRAMEDONE to know
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- * that DISPC has finished with the LCD output.
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- */
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-
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- irq = dispc_mgr_get_framedone_irq(channel);
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-
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- r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
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- irq);
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- if (r)
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- DSSERR("failed to register FRAMEDONE isr\n");
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-
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- dispc_mgr_enable(channel, false);
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-
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- /* if we couldn't register for framedone, just sleep and exit */
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- if (r) {
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- msleep(100);
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- return;
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- }
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-
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- if (!wait_for_completion_timeout(&framedone_compl,
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- msecs_to_jiffies(100)))
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- DSSERR("timeout waiting for FRAME DONE\n");
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-
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- r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
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- irq);
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- if (r)
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- DSSERR("failed to unregister FRAMEDONE isr\n");
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-}
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-
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-static void dispc_digit_out_enable_isr(void *data, u32 mask)
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-{
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- struct completion *compl = data;
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-
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- /* ignore any sync lost interrupts */
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- if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
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- complete(compl);
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-}
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-
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-static void dispc_mgr_enable_digit_out(void)
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-{
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- DECLARE_COMPLETION_ONSTACK(vsync_compl);
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- int r;
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- u32 irq_mask;
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-
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- if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
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- return;
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-
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- /*
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- * Digit output produces some sync lost interrupts during the first
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- * frame when enabling. Those need to be ignored, so we register for the
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- * sync lost irq to prevent the error handler from triggering.
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- */
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-
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- irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
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- dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
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-
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- r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
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- irq_mask);
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- if (r) {
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- DSSERR("failed to register %x isr\n", irq_mask);
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- return;
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- }
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-
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- dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, true);
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-
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- /* wait for the first evsync */
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- if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
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- DSSERR("timeout waiting for digit out to start\n");
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-
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- r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
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- irq_mask);
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- if (r)
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- DSSERR("failed to unregister %x isr\n", irq_mask);
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-}
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-
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-static void dispc_mgr_disable_digit_out(void)
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-{
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- DECLARE_COMPLETION_ONSTACK(framedone_compl);
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- int r, i;
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- u32 irq_mask;
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- int num_irqs;
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-
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- if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
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- return;
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-
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- /*
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- * When we disable the digit output, we need to wait for FRAMEDONE to
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- * know that DISPC has finished with the output.
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- */
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-
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- irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
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- num_irqs = 1;
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-
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- if (!irq_mask) {
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- /*
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- * omap 2/3 don't have framedone irq for TV, so we need to use
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- * vsyncs for this.
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- */
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-
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- irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
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- /*
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- * We need to wait for both even and odd vsyncs. Note that this
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- * is not totally reliable, as we could get a vsync interrupt
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- * before we disable the output, which leads to timeout in the
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- * wait_for_completion.
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- */
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- num_irqs = 2;
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- }
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-
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- r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
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- irq_mask);
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- if (r)
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- DSSERR("failed to register %x isr\n", irq_mask);
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-
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- dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, false);
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-
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- /* if we couldn't register the irq, just sleep and exit */
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- if (r) {
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- msleep(100);
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- return;
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- }
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-
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- for (i = 0; i < num_irqs; ++i) {
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- if (!wait_for_completion_timeout(&framedone_compl,
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- msecs_to_jiffies(100)))
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- DSSERR("timeout waiting for digit out to stop\n");
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- }
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-
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- r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
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- irq_mask);
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- if (r)
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- DSSERR("failed to unregister %x isr\n", irq_mask);
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-}
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-
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-void dispc_mgr_enable_sync(enum omap_channel channel)
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-{
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- if (dss_mgr_is_lcd(channel))
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- dispc_mgr_enable_lcd_out(channel);
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- else if (channel == OMAP_DSS_CHANNEL_DIGIT)
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- dispc_mgr_enable_digit_out();
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- else
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- WARN_ON(1);
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-}
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-
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-void dispc_mgr_disable_sync(enum omap_channel channel)
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-{
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- if (dss_mgr_is_lcd(channel))
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- dispc_mgr_disable_lcd_out(channel);
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- else if (channel == OMAP_DSS_CHANNEL_DIGIT)
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- dispc_mgr_disable_digit_out();
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- else
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- WARN_ON(1);
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-}
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+EXPORT_SYMBOL(dispc_mgr_is_enabled);
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void dispc_wb_enable(bool enable)
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{
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@@ -2881,6 +2726,7 @@ void dispc_mgr_setup(enum omap_channel channel,
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dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
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}
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}
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+EXPORT_SYMBOL(dispc_mgr_setup);
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static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
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{
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@@ -2957,6 +2803,7 @@ void dispc_mgr_set_lcd_config(enum omap_channel channel,
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dispc_mgr_set_lcd_type_tft(channel);
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}
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+EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
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static bool _dispc_mgr_size_ok(u16 width, u16 height)
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{
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@@ -3095,6 +2942,7 @@ void dispc_mgr_set_timings(enum omap_channel channel,
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dispc_mgr_set_size(channel, t.x_res, t.y_res);
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}
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+EXPORT_SYMBOL(dispc_mgr_set_timings);
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static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
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u16 pck_div)
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@@ -3301,64 +3149,6 @@ void dispc_dump_clocks(struct seq_file *s)
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dispc_runtime_put();
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}
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-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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-static void dispc_dump_irqs(struct seq_file *s)
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-{
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- unsigned long flags;
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- struct dispc_irq_stats stats;
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-
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- spin_lock_irqsave(&dispc.irq_stats_lock, flags);
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-
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- stats = dispc.irq_stats;
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- memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
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- dispc.irq_stats.last_reset = jiffies;
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-
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- spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
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-
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- seq_printf(s, "period %u ms\n",
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- jiffies_to_msecs(jiffies - stats.last_reset));
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-
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- seq_printf(s, "irqs %d\n", stats.irq_count);
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-#define PIS(x) \
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- seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
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-
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- PIS(FRAMEDONE);
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- PIS(VSYNC);
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- PIS(EVSYNC_EVEN);
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- PIS(EVSYNC_ODD);
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- PIS(ACBIAS_COUNT_STAT);
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- PIS(PROG_LINE_NUM);
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- PIS(GFX_FIFO_UNDERFLOW);
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- PIS(GFX_END_WIN);
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- PIS(PAL_GAMMA_MASK);
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- PIS(OCP_ERR);
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- PIS(VID1_FIFO_UNDERFLOW);
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- PIS(VID1_END_WIN);
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- PIS(VID2_FIFO_UNDERFLOW);
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- PIS(VID2_END_WIN);
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- if (dss_feat_get_num_ovls() > 3) {
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- PIS(VID3_FIFO_UNDERFLOW);
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- PIS(VID3_END_WIN);
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- }
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- PIS(SYNC_LOST);
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- PIS(SYNC_LOST_DIGIT);
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- PIS(WAKEUP);
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- if (dss_has_feature(FEAT_MGR_LCD2)) {
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- PIS(FRAMEDONE2);
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- PIS(VSYNC2);
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- PIS(ACBIAS_COUNT_STAT2);
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- PIS(SYNC_LOST2);
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- }
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- if (dss_has_feature(FEAT_MGR_LCD3)) {
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- PIS(FRAMEDONE3);
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- PIS(VSYNC3);
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- PIS(ACBIAS_COUNT_STAT3);
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- PIS(SYNC_LOST3);
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- }
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-#undef PIS
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-}
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-#endif
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-
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static void dispc_dump_regs(struct seq_file *s)
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{
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int i, j;
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@@ -3616,16 +3406,19 @@ u32 dispc_read_irqstatus(void)
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{
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return dispc_read_reg(DISPC_IRQSTATUS);
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}
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+EXPORT_SYMBOL(dispc_read_irqstatus);
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void dispc_clear_irqstatus(u32 mask)
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{
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dispc_write_reg(DISPC_IRQSTATUS, mask);
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}
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+EXPORT_SYMBOL(dispc_clear_irqstatus);
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u32 dispc_read_irqenable(void)
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{
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return dispc_read_reg(DISPC_IRQENABLE);
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}
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+EXPORT_SYMBOL(dispc_read_irqenable);
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void dispc_write_irqenable(u32 mask)
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{
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@@ -3636,376 +3429,7 @@ void dispc_write_irqenable(u32 mask)
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dispc_write_reg(DISPC_IRQENABLE, mask);
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}
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-
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-/* dispc.irq_lock has to be locked by the caller */
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-static void _omap_dispc_set_irqs(void)
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-{
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- u32 mask;
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- int i;
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- struct omap_dispc_isr_data *isr_data;
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-
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- mask = dispc.irq_error_mask;
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-
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- for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
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- isr_data = &dispc.registered_isr[i];
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-
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- if (isr_data->isr == NULL)
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- continue;
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-
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- mask |= isr_data->mask;
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- }
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-
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- dispc_write_irqenable(mask);
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-}
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-
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-int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
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-{
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- int i;
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- int ret;
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- unsigned long flags;
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- struct omap_dispc_isr_data *isr_data;
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-
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- if (isr == NULL)
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- return -EINVAL;
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-
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- spin_lock_irqsave(&dispc.irq_lock, flags);
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-
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- /* check for duplicate entry */
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- for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
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- isr_data = &dispc.registered_isr[i];
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- if (isr_data->isr == isr && isr_data->arg == arg &&
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- isr_data->mask == mask) {
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- ret = -EINVAL;
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- goto err;
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- }
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- }
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-
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- isr_data = NULL;
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- ret = -EBUSY;
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-
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- for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
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- isr_data = &dispc.registered_isr[i];
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-
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- if (isr_data->isr != NULL)
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- continue;
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-
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- isr_data->isr = isr;
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- isr_data->arg = arg;
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- isr_data->mask = mask;
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- ret = 0;
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-
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- break;
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- }
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-
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- if (ret)
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- goto err;
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-
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- _omap_dispc_set_irqs();
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-
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- spin_unlock_irqrestore(&dispc.irq_lock, flags);
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-
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- return 0;
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-err:
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- spin_unlock_irqrestore(&dispc.irq_lock, flags);
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-
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- return ret;
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-}
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-EXPORT_SYMBOL(omap_dispc_register_isr);
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-
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-int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
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-{
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- int i;
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- unsigned long flags;
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- int ret = -EINVAL;
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- struct omap_dispc_isr_data *isr_data;
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-
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- spin_lock_irqsave(&dispc.irq_lock, flags);
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-
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- for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
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- isr_data = &dispc.registered_isr[i];
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- if (isr_data->isr != isr || isr_data->arg != arg ||
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- isr_data->mask != mask)
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- continue;
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-
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- /* found the correct isr */
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-
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- isr_data->isr = NULL;
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- isr_data->arg = NULL;
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- isr_data->mask = 0;
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-
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- ret = 0;
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- break;
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- }
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-
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- if (ret == 0)
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- _omap_dispc_set_irqs();
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-
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- spin_unlock_irqrestore(&dispc.irq_lock, flags);
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-
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- return ret;
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-}
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-EXPORT_SYMBOL(omap_dispc_unregister_isr);
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-
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-static void print_irq_status(u32 status)
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-{
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- if ((status & dispc.irq_error_mask) == 0)
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- return;
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-
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-#define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : ""
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-
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- pr_debug("DISPC IRQ: 0x%x: %s%s%s%s%s%s%s%s%s\n",
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- status,
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- PIS(OCP_ERR),
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- PIS(GFX_FIFO_UNDERFLOW),
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- PIS(VID1_FIFO_UNDERFLOW),
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- PIS(VID2_FIFO_UNDERFLOW),
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- dss_feat_get_num_ovls() > 3 ? PIS(VID3_FIFO_UNDERFLOW) : "",
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- PIS(SYNC_LOST),
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- PIS(SYNC_LOST_DIGIT),
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- dss_has_feature(FEAT_MGR_LCD2) ? PIS(SYNC_LOST2) : "",
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- dss_has_feature(FEAT_MGR_LCD3) ? PIS(SYNC_LOST3) : "");
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-#undef PIS
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-}
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-
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-/* Called from dss.c. Note that we don't touch clocks here,
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- * but we presume they are on because we got an IRQ. However,
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- * an irq handler may turn the clocks off, so we may not have
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- * clock later in the function. */
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-static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
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-{
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- int i;
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- u32 irqstatus, irqenable;
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- u32 handledirqs = 0;
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- u32 unhandled_errors;
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- struct omap_dispc_isr_data *isr_data;
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- struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
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-
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- spin_lock(&dispc.irq_lock);
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-
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- irqstatus = dispc_read_irqstatus();
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- irqenable = dispc_read_irqenable();
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-
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- /* IRQ is not for us */
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- if (!(irqstatus & irqenable)) {
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- spin_unlock(&dispc.irq_lock);
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- return IRQ_NONE;
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- }
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-
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-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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- spin_lock(&dispc.irq_stats_lock);
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- dispc.irq_stats.irq_count++;
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- dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
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- spin_unlock(&dispc.irq_stats_lock);
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-#endif
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-
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- print_irq_status(irqstatus);
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-
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- /* Ack the interrupt. Do it here before clocks are possibly turned
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- * off */
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- dispc_clear_irqstatus(irqstatus);
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- /* flush posted write */
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- dispc_read_irqstatus();
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-
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- /* make a copy and unlock, so that isrs can unregister
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- * themselves */
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- memcpy(registered_isr, dispc.registered_isr,
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- sizeof(registered_isr));
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-
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- spin_unlock(&dispc.irq_lock);
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-
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- for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
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- isr_data = ®istered_isr[i];
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-
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- if (!isr_data->isr)
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- continue;
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-
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- if (isr_data->mask & irqstatus) {
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- isr_data->isr(isr_data->arg, irqstatus);
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- handledirqs |= isr_data->mask;
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- }
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- }
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-
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- spin_lock(&dispc.irq_lock);
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-
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- unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
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-
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- if (unhandled_errors) {
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- dispc.error_irqs |= unhandled_errors;
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-
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- dispc.irq_error_mask &= ~unhandled_errors;
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- _omap_dispc_set_irqs();
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-
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- schedule_work(&dispc.error_work);
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- }
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-
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- spin_unlock(&dispc.irq_lock);
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-
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- return IRQ_HANDLED;
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-}
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-
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-static void dispc_error_worker(struct work_struct *work)
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-{
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- int i;
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- u32 errors;
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- unsigned long flags;
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- static const unsigned fifo_underflow_bits[] = {
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- DISPC_IRQ_GFX_FIFO_UNDERFLOW,
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- DISPC_IRQ_VID1_FIFO_UNDERFLOW,
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- DISPC_IRQ_VID2_FIFO_UNDERFLOW,
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- DISPC_IRQ_VID3_FIFO_UNDERFLOW,
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- };
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-
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- spin_lock_irqsave(&dispc.irq_lock, flags);
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- errors = dispc.error_irqs;
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- dispc.error_irqs = 0;
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- spin_unlock_irqrestore(&dispc.irq_lock, flags);
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-
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- dispc_runtime_get();
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-
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- for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
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- struct omap_overlay *ovl;
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- unsigned bit;
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-
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- ovl = omap_dss_get_overlay(i);
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- bit = fifo_underflow_bits[i];
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-
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- if (bit & errors) {
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- DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
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- ovl->name);
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- dispc_ovl_enable(ovl->id, false);
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- dispc_mgr_go(ovl->manager->id);
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- msleep(50);
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- }
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- }
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-
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- for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
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- struct omap_overlay_manager *mgr;
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- unsigned bit;
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-
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- mgr = omap_dss_get_overlay_manager(i);
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- bit = mgr_desc[i].sync_lost_irq;
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-
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- if (bit & errors) {
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- int j;
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-
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- DSSERR("SYNC_LOST on channel %s, restarting the output "
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- "with video overlays disabled\n",
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- mgr->name);
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-
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- dss_mgr_disable(mgr);
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-
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- for (j = 0; j < omap_dss_get_num_overlays(); ++j) {
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- struct omap_overlay *ovl;
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- ovl = omap_dss_get_overlay(j);
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-
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- if (ovl->id != OMAP_DSS_GFX &&
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- ovl->manager == mgr)
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- ovl->disable(ovl);
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- }
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-
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- dss_mgr_enable(mgr);
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- }
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- }
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-
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- if (errors & DISPC_IRQ_OCP_ERR) {
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- DSSERR("OCP_ERR\n");
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- for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
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- struct omap_overlay_manager *mgr;
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-
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- mgr = omap_dss_get_overlay_manager(i);
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- dss_mgr_disable(mgr);
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- }
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- }
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-
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- spin_lock_irqsave(&dispc.irq_lock, flags);
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- dispc.irq_error_mask |= errors;
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- _omap_dispc_set_irqs();
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- spin_unlock_irqrestore(&dispc.irq_lock, flags);
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-
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- dispc_runtime_put();
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-}
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-
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-int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
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-{
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- void dispc_irq_wait_handler(void *data, u32 mask)
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- {
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- complete((struct completion *)data);
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- }
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-
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- int r;
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- DECLARE_COMPLETION_ONSTACK(completion);
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-
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- r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
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- irqmask);
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-
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- if (r)
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- return r;
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-
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- timeout = wait_for_completion_timeout(&completion, timeout);
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-
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- omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
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-
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- if (timeout == 0)
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- return -ETIMEDOUT;
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-
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- return 0;
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-}
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-
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-int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
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- unsigned long timeout)
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-{
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- void dispc_irq_wait_handler(void *data, u32 mask)
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- {
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- complete((struct completion *)data);
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- }
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-
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- int r;
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- DECLARE_COMPLETION_ONSTACK(completion);
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-
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- r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
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- irqmask);
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-
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- if (r)
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- return r;
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-
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- timeout = wait_for_completion_interruptible_timeout(&completion,
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- timeout);
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-
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- omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
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-
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- if (timeout == 0)
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- return -ETIMEDOUT;
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-
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- if (timeout == -ERESTARTSYS)
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- return -ERESTARTSYS;
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-
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- return 0;
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-}
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-
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-static void _omap_dispc_initialize_irq(void)
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-{
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- unsigned long flags;
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-
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- spin_lock_irqsave(&dispc.irq_lock, flags);
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-
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- memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
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-
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- dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
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- if (dss_has_feature(FEAT_MGR_LCD2))
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- dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
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- if (dss_has_feature(FEAT_MGR_LCD3))
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- dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
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- if (dss_feat_get_num_ovls() > 3)
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- dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
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-
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- /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
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- * so clear it */
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- dispc_clear_irqstatus(dispc_read_irqstatus());
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-
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- _omap_dispc_set_irqs();
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-
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- spin_unlock_irqrestore(&dispc.irq_lock, flags);
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-}
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+EXPORT_SYMBOL(dispc_write_irqenable);
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void dispc_enable_sidle(void)
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{
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@@ -4176,6 +3600,19 @@ static int __init dispc_init_features(struct platform_device *pdev)
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return 0;
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}
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+int dispc_request_irq(irq_handler_t handler, void *dev_id)
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+{
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+ return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler,
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+ IRQF_SHARED, "OMAP DISPC", dev_id);
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+}
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+EXPORT_SYMBOL(dispc_request_irq);
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+
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+void dispc_free_irq(void *dev_id)
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+{
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+ devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id);
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+}
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+EXPORT_SYMBOL(dispc_free_irq);
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+
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/* DISPC HW IP initialisation */
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static int __init omap_dispchw_probe(struct platform_device *pdev)
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{
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@@ -4190,15 +3627,6 @@ static int __init omap_dispchw_probe(struct platform_device *pdev)
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if (r)
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return r;
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- spin_lock_init(&dispc.irq_lock);
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-
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-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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- spin_lock_init(&dispc.irq_stats_lock);
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- dispc.irq_stats.last_reset = jiffies;
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-#endif
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-
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- INIT_WORK(&dispc.error_work, dispc_error_worker);
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-
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dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
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if (!dispc_mem) {
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DSSERR("can't get IORESOURCE_MEM DISPC\n");
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@@ -4218,13 +3646,6 @@ static int __init omap_dispchw_probe(struct platform_device *pdev)
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return -ENODEV;
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}
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- r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
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- IRQF_SHARED, "OMAP DISPC", dispc.pdev);
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- if (r < 0) {
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- DSSERR("request_irq failed\n");
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- return r;
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- }
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-
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clk = clk_get(&pdev->dev, "fck");
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if (IS_ERR(clk)) {
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DSSERR("can't get fck\n");
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@@ -4242,8 +3663,6 @@ static int __init omap_dispchw_probe(struct platform_device *pdev)
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_omap_dispc_initial_config();
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- _omap_dispc_initialize_irq();
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-
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rev = dispc_read_reg(DISPC_REVISION);
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dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
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FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
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@@ -4252,9 +3671,6 @@ static int __init omap_dispchw_probe(struct platform_device *pdev)
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dss_debugfs_create_file("dispc", dispc_dump_regs);
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-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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- dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
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-#endif
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return 0;
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err_runtime_get:
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Tomi Valkeinen