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@@ -135,10 +135,6 @@
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#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
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#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
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#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
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#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
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-#define S3C2410_UDC_SETIX(base,x) \
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- writel(S3C2410_UDC_INDEX_ ## x, base+S3C2410_UDC_INDEX_REG);
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-
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-
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#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
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#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
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#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
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#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
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#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
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#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
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