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@@ -48,7 +48,7 @@
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#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
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#define DMA_2W_BURST BIT(1) /* 2 word burst length */
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#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
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-#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */
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+#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
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#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
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#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
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@@ -191,10 +191,10 @@ ltq_dma_init_port(int p)
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switch (p) {
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case DMA_PORT_ETOP:
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/*
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- * Tell the DMA engine to swap the endianess of data frames and
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+ * Tell the DMA engine to swap the endianness of data frames and
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* drop packets if the channel arbitration fails.
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*/
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- ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN,
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+ ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
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LTQ_DMA_PCTRL);
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break;
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