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@@ -131,8 +131,6 @@ static void free_skb_resources(struct gfar_private *priv);
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static void gfar_set_multi(struct net_device *dev);
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static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
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static void gfar_configure_serdes(struct net_device *dev);
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-extern int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id, int regnum, u16 value);
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-extern int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum);
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#ifdef CONFIG_GFAR_NAPI
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static int gfar_poll(struct napi_struct *napi, int budget);
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#endif
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@@ -477,24 +475,30 @@ static int init_phy(struct net_device *dev)
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return 0;
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}
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+/*
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+ * Initialize TBI PHY interface for communicating with the
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+ * SERDES lynx PHY on the chip. We communicate with this PHY
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+ * through the MDIO bus on each controller, treating it as a
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+ * "normal" PHY at the address found in the TBIPA register. We assume
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+ * that the TBIPA register is valid. Either the MDIO bus code will set
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+ * it to a value that doesn't conflict with other PHYs on the bus, or the
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+ * value doesn't matter, as there are no other PHYs on the bus.
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+ */
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static void gfar_configure_serdes(struct net_device *dev)
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{
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struct gfar_private *priv = netdev_priv(dev);
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struct gfar_mii __iomem *regs =
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(void __iomem *)&priv->regs->gfar_mii_regs;
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+ int tbipa = gfar_read(&priv->regs->tbipa);
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- /* Initialise TBI i/f to communicate with serdes (lynx phy) */
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+ /* Single clk mode, mii mode off(for serdes communication) */
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+ gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
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- /* Single clk mode, mii mode off(for aerdes communication) */
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- gfar_local_mdio_write(regs, TBIPA_VALUE, MII_TBICON, TBICON_CLK_SELECT);
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-
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- /* Supported pause and full-duplex, no half-duplex */
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- gfar_local_mdio_write(regs, TBIPA_VALUE, MII_ADVERTISE,
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+ gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
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ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
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ADVERTISE_1000XPSE_ASYM);
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- /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
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- gfar_local_mdio_write(regs, TBIPA_VALUE, MII_BMCR, BMCR_ANENABLE |
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+ gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
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BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
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}
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@@ -541,9 +545,6 @@ static void init_registers(struct net_device *dev)
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/* Initialize the Minimum Frame Length Register */
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gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
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-
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- /* Assign the TBI an address which won't conflict with the PHYs */
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- gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
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}
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