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@@ -45,6 +45,7 @@
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#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
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/* Media-dependent registers. */
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+#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
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#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
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* Lanes B-D are numbered 134-136. */
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@@ -195,6 +196,14 @@
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#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
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#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
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+/* PMA 10GBASE-T pair swap & polarity */
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+#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */
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+#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */
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+#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */
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+#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */
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+#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */
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+#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */
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+
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/* PMA 10GBASE-T TX power register. */
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#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
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