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@@ -48,7 +48,7 @@ static struct clk r_clk = {
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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-struct clk extal_clk = {
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+static struct clk extal_clk = {
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.rate = 33333333,
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};
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@@ -111,7 +111,7 @@ static struct clk div3_clk = {
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.parent = &pll_clk,
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};
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-struct clk *main_clks[] = {
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+static struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&fll_clk,
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@@ -156,7 +156,7 @@ struct clk div4_clks[DIV4_NR] = {
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enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
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-struct clk div6_clks[DIV6_NR] = {
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+static struct clk div6_clks[DIV6_NR] = {
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[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
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[DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
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[DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
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