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@@ -405,6 +405,14 @@ static int ironlake_do_reset(struct drm_device *dev, u8 flags)
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return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
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return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
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}
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}
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+static int gen6_do_reset(struct drm_device *dev, u8 flags)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+
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+ I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
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+ return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
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+}
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+
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/**
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/**
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* i965_reset - reset chip after a hang
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* i965_reset - reset chip after a hang
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* @dev: drm device to reset
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* @dev: drm device to reset
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@@ -439,6 +447,9 @@ int i915_reset(struct drm_device *dev, u8 flags)
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if (get_seconds() - dev_priv->last_gpu_reset < 5) {
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if (get_seconds() - dev_priv->last_gpu_reset < 5) {
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DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
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DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
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} else switch (INTEL_INFO(dev)->gen) {
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} else switch (INTEL_INFO(dev)->gen) {
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+ case 6:
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+ ret = gen6_do_reset(dev, flags);
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+ break;
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case 5:
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case 5:
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ret = ironlake_do_reset(dev, flags);
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ret = ironlake_do_reset(dev, flags);
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break;
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break;
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