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@@ -646,6 +646,15 @@ DEFINE_DEV_DATA(macb, 0);
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DEV_CLK(hclk, macb0, hsb, 8);
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DEV_CLK(pclk, macb0, pbb, 6);
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+static struct eth_platform_data macb1_data;
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+static struct resource macb1_resource[] = {
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+ PBMEM(0xfff01c00),
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+ IRQ(26),
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+};
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+DEFINE_DEV_DATA(macb, 1);
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+DEV_CLK(hclk, macb1, hsb, 9);
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+DEV_CLK(pclk, macb1, pbb, 7);
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+
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struct platform_device *__init
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at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
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{
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@@ -679,6 +688,33 @@ at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
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}
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break;
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+ case 1:
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+ pdev = &macb1_device;
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+
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+ select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
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+ select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
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+ select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
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+ select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
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+ select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
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+ select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
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+ select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
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+ select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
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+ select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
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+ select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
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+
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+ if (!data->is_rmii) {
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+ select_peripheral(PC(19), PERIPH_B, 0); /* COL */
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+ select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
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+ select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
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+ select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
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+ select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
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+ select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
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+ select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
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+ select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
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+ select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
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+ }
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+ break;
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+
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default:
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return NULL;
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}
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@@ -830,6 +866,8 @@ struct clk *at32_clock_list[] = {
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&atmel_usart3_usart,
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&macb0_hclk,
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&macb0_pclk,
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+ &macb1_hclk,
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+ &macb1_pclk,
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&spi0_mck,
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&lcdc0_hclk,
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&lcdc0_pixclk,
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