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@@ -104,7 +104,6 @@ static const int txqaddr[] = { Q_XA1, Q_XA2 };
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static const int rxqaddr[] = { Q_R1, Q_R2 };
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static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
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static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
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-static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
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static int skge_get_regs_len(struct net_device *dev)
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{
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@@ -2184,12 +2183,6 @@ static int skge_up(struct net_device *dev)
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skge->tx_avail = skge->tx_ring.count - 1;
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- /* Enable IRQ from port */
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- spin_lock_irq(&hw->hw_lock);
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- hw->intr_mask |= portirqmask[port];
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- skge_write32(hw, B0_IMSK, hw->intr_mask);
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- spin_unlock_irq(&hw->hw_lock);
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-
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/* Initialize MAC */
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spin_lock_bh(&hw->phy_lock);
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if (hw->chip_id == CHIP_ID_GENESIS)
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@@ -2246,11 +2239,6 @@ static int skge_down(struct net_device *dev)
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else
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yukon_stop(skge);
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- spin_lock_irq(&hw->hw_lock);
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- hw->intr_mask &= ~portirqmask[skge->port];
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- skge_write32(hw, B0_IMSK, hw->intr_mask);
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- spin_unlock_irq(&hw->hw_lock);
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-
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/* Stop transmitter */
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skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
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skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
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@@ -2734,11 +2722,9 @@ static int skge_poll(struct net_device *dev, int *budget)
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if (work_done >= to_do)
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return 1; /* not done */
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- spin_lock_irq(&hw->hw_lock);
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- __netif_rx_complete(dev);
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- hw->intr_mask |= portirqmask[skge->port];
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+ netif_rx_complete(dev);
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+ hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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- spin_unlock_irq(&hw->hw_lock);
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return 0;
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}
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@@ -2850,12 +2836,11 @@ static void skge_extirq(unsigned long data)
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int port;
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spin_lock(&hw->phy_lock);
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- for (port = 0; port < 2; port++) {
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+ for (port = 0; port < hw->ports; port++) {
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struct net_device *dev = hw->dev[port];
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+ struct skge_port *skge = netdev_priv(dev);
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- if (dev && netif_running(dev)) {
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- struct skge_port *skge = netdev_priv(dev);
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-
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+ if (netif_running(dev)) {
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if (hw->chip_id != CHIP_ID_GENESIS)
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yukon_phy_intr(skge);
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else
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@@ -2864,21 +2849,25 @@ static void skge_extirq(unsigned long data)
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}
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spin_unlock(&hw->phy_lock);
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- spin_lock_irq(&hw->hw_lock);
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hw->intr_mask |= IS_EXT_REG;
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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- spin_unlock_irq(&hw->hw_lock);
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}
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static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct skge_hw *hw = dev_id;
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- u32 status = skge_read32(hw, B0_SP_ISRC);
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+ u32 status;
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- if (status == 0 || status == ~0) /* hotplug or shared irq */
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+ /* Reading this register masks IRQ */
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+ status = skge_read32(hw, B0_SP_ISRC);
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+ if (status == 0)
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return IRQ_NONE;
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- spin_lock(&hw->hw_lock);
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+ if (status & IS_EXT_REG) {
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+ hw->intr_mask &= ~IS_EXT_REG;
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+ tasklet_schedule(&hw->ext_tasklet);
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+ }
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+
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if (status & (IS_R1_F|IS_XA1_F)) {
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skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
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hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);
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@@ -2891,6 +2880,9 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
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netif_rx_schedule(hw->dev[1]);
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}
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+ if (likely((status & hw->intr_mask) == 0))
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+ return IRQ_HANDLED;
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+
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if (status & IS_PA_TO_RX1) {
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struct skge_port *skge = netdev_priv(hw->dev[0]);
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++skge->net_stats.rx_over_errors;
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@@ -2918,13 +2910,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
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if (status & IS_HW_ERR)
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skge_error_irq(hw);
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- if (status & IS_EXT_REG) {
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- hw->intr_mask &= ~IS_EXT_REG;
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- tasklet_schedule(&hw->ext_tasklet);
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- }
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-
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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- spin_unlock(&hw->hw_lock);
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return IRQ_HANDLED;
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}
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@@ -3070,7 +3056,10 @@ static int skge_reset(struct skge_hw *hw)
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else
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hw->ram_size = t8 * 4096;
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- hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
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+ hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
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+ if (hw->ports > 1)
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+ hw->intr_mask |= IS_PORT_2;
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+
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if (hw->chip_id == CHIP_ID_GENESIS)
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genesis_init(hw);
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else {
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@@ -3293,7 +3282,6 @@ static int __devinit skge_probe(struct pci_dev *pdev,
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hw->pdev = pdev;
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spin_lock_init(&hw->phy_lock);
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- spin_lock_init(&hw->hw_lock);
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tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
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hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
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