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@@ -685,6 +685,8 @@ void __init find_smp_config(void)
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#ifdef CONFIG_ACPI
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+#ifdef CONFIG_X86_IO_APIC
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+
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#define MP_ISA_BUS 0
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#define MP_MAX_IOAPIC_PIN 127
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@@ -770,7 +772,7 @@ void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
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int ioapic = -1;
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int pin = -1;
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- /*
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+ /*
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* Convert 'gsi' to 'ioapic.pin'.
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*/
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ioapic = mp_find_ioapic(gsi);
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@@ -780,7 +782,7 @@ void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
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/*
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* TBD: This check is for faulty timer entries, where the override
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- * erroneously sets the trigger to level, resulting in a HUGE
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+ * erroneously sets the trigger to level, resulting in a HUGE
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* increase of timer interrupts!
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*/
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if ((bus_irq == 0) && (trigger == 3))
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@@ -886,9 +888,22 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
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int ioapic = -1;
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int ioapic_pin = 0;
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int idx, bit = 0;
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+#ifdef CONFIG_X86_32
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+#define MAX_GSI_NUM 4096
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+#define IRQ_COMPRESSION_START 64
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+
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+ static int pci_irq = IRQ_COMPRESSION_START;
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+ /*
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+ * Mapping between Global System Interrupts, which
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+ * represent all possible interrupts, and IRQs
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+ * assigned to actual devices.
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+ */
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+ static int gsi_to_irq[MAX_GSI_NUM];
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+#else
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if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
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return gsi;
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+#endif
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/* Don't set up the ACPI SCI because it's already set up */
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if (acpi_gbl_FADT.sci_interrupt == gsi)
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@@ -902,8 +917,13 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
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ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
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- /*
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- * Avoid pin reprogramming. PRTs typically include entries
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+#ifdef CONFIG_X86_32
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+ if (ioapic_renumber_irq)
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+ gsi = ioapic_renumber_irq(ioapic, gsi);
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+#endif
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+
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+ /*
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+ * Avoid pin reprogramming. PRTs typically include entries
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* with redundant pin->gsi mappings (but unique PCI devices);
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* we only program the IOAPIC on the first.
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*/
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@@ -918,14 +938,54 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
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if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
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Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
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mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
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+#ifdef CONFIG_X86_32
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+ return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
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+#else
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return gsi;
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+#endif
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}
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mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit);
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-
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+#ifdef CONFIG_X86_32
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+ /*
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+ * For GSI >= 64, use IRQ compression
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+ */
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+ if ((gsi >= IRQ_COMPRESSION_START)
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+ && (triggering == ACPI_LEVEL_SENSITIVE)) {
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+ /*
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+ * For PCI devices assign IRQs in order, avoiding gaps
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+ * due to unused I/O APIC pins.
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+ */
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+ int irq = gsi;
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+ if (gsi < MAX_GSI_NUM) {
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+ /*
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+ * Retain the VIA chipset work-around (gsi > 15), but
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+ * avoid a problem where the 8254 timer (IRQ0) is setup
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+ * via an override (so it's not on pin 0 of the ioapic),
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+ * and at the same time, the pin 0 interrupt is a PCI
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+ * type. The gsi > 15 test could cause these two pins
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+ * to be shared as IRQ0, and they are not shareable.
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+ * So test for this condition, and if necessary, avoid
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+ * the pin collision.
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+ */
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+ gsi = pci_irq++;
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+ /*
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+ * Don't assign IRQ used by ACPI SCI
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+ */
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+ if (gsi == acpi_gbl_FADT.sci_interrupt)
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+ gsi = pci_irq++;
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+ gsi_to_irq[irq] = gsi;
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+ } else {
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+ printk(KERN_ERR "GSI %u is too high\n", gsi);
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+ return gsi;
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+ }
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+ }
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+#endif
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io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
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triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
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polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
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return gsi;
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}
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+
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+#endif /* CONFIG_X86_IO_APIC */
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#endif /* CONFIG_ACPI */
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