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@@ -64,6 +64,7 @@
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#include <linux/pci-aspm.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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+#include <linux/sched.h>
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#include <linux/bitops.h>
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#include <linux/gfp.h>
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@@ -895,7 +896,79 @@ static const u8 iwlagn_pan_ac_to_queue[] = {
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7, 6, 5, 4,
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};
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-static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
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+/*
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+ * ucode
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+ */
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+static int iwl_load_section(struct iwl_trans *trans, const char *name,
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+ struct fw_desc *image, u32 dst_addr)
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+{
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+ dma_addr_t phy_addr = image->p_addr;
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+ u32 byte_cnt = image->len;
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+ int ret;
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+
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+ trans->ucode_write_complete = 0;
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+
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+ iwl_write_direct32(trans,
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+ FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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+ FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
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+
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+ iwl_write_direct32(trans,
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+ FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
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+
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+ iwl_write_direct32(trans,
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+ FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
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+ phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
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+
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+ iwl_write_direct32(trans,
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+ FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
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+ (iwl_get_dma_hi_addr(phy_addr)
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+ << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
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+
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+ iwl_write_direct32(trans,
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+ FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
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+ 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
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+ 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
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+ FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
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+
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+ iwl_write_direct32(trans,
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+ FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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+ FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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+ FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
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+ FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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+
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+ IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
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+ ret = wait_event_timeout(trans->shrd->wait_command_queue,
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+ trans->ucode_write_complete, 5 * HZ);
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+ if (!ret) {
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+ IWL_ERR(trans, "Could not load the %s uCode section\n",
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+ name);
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+ return -ETIMEDOUT;
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+ }
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+
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+ return 0;
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+}
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+
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+static int iwl_load_given_ucode(struct iwl_trans *trans, struct fw_img *image)
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+{
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+ int ret = 0;
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+
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+ ret = iwl_load_section(trans, "INST", &image->code,
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+ IWLAGN_RTC_INST_LOWER_BOUND);
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+ if (ret)
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+ return ret;
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+
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+ ret = iwl_load_section(trans, "DATA", &image->data,
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+ IWLAGN_RTC_DATA_LOWER_BOUND);
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+ if (ret)
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+ return ret;
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+
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+ /* Remove all resets to allow NIC to operate */
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+ iwl_write32(trans, CSR_RESET, 0);
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+
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+ return 0;
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+}
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+
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+static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, struct fw_img *fw)
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{
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int ret;
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struct iwl_trans_pcie *trans_pcie =
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@@ -951,6 +1024,9 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
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iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
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iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
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+ /* Load the given image to the HW */
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+ iwl_load_given_ucode(trans, fw);
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+
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return 0;
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}
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@@ -1353,12 +1429,6 @@ static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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return 0;
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}
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-static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
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-{
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- /* Remove all resets to allow NIC to operate */
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- iwl_write32(trans, CSR_RESET, 0);
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-}
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-
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static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie =
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@@ -2086,7 +2156,7 @@ const struct iwl_trans_ops trans_ops_pcie = {
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.start_hw = iwl_trans_pcie_start_hw,
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.stop_hw = iwl_trans_pcie_stop_hw,
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.fw_alive = iwl_trans_pcie_fw_alive,
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- .start_device = iwl_trans_pcie_start_device,
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+ .start_fw = iwl_trans_pcie_start_fw,
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.stop_device = iwl_trans_pcie_stop_device,
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.wake_any_queue = iwl_trans_pcie_wake_any_queue,
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@@ -2100,8 +2170,6 @@ const struct iwl_trans_ops trans_ops_pcie = {
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.tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
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.tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
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- .kick_nic = iwl_trans_pcie_kick_nic,
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-
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.free = iwl_trans_pcie_free,
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.stop_queue = iwl_trans_pcie_stop_queue,
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