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@@ -4143,6 +4143,23 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
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struct drm_device *dev = crtc->base.dev;
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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+ if (INTEL_INFO(dev)->gen < 4) {
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ int clock_limit =
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+ dev_priv->display.get_display_clock_speed(dev);
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+
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+ /*
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+ * Enable pixel doubling when the dot clock
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+ * is > 90% of the (display) core speed.
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+ *
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+ * XXX: No double-wide on 915GM pipe B. Is that
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+ * the only reason for the pipe == PIPE_A check?
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+ */
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+ if (crtc->pipe == PIPE_A &&
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+ adjusted_mode->clock > clock_limit * 9 / 10)
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+ pipe_config->double_wide = true;
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+ }
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+
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/* Cantiga+ cannot handle modes with a hsync front porch of 0.
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* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
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*/
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@@ -4801,17 +4818,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
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pipeconf = 0;
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- if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
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- /* Enable pixel doubling when the dot clock is > 90% of the (display)
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- * core speed.
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- *
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- * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
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- * pipe == 0 check?
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- */
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- if (intel_crtc->config.adjusted_mode.clock >
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- dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
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- pipeconf |= PIPECONF_DOUBLE_WIDE;
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- }
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+ if (intel_crtc->config.double_wide)
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+ pipeconf |= PIPECONF_DOUBLE_WIDE;
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/* only g4x and later have fancy bpc/dither controls */
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if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
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@@ -8336,6 +8344,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
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pipe_config->pch_pfit.pos,
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pipe_config->pch_pfit.size);
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DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
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+ DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
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}
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static bool check_encoder_cloning(struct drm_crtc *crtc)
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