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@@ -44,10 +44,21 @@
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#define TCFG1_SHIFT(x) ((x) * 4)
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#define TCFG1_MUX_MASK 0xf
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+/*
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+ * Each channel occupies 4 bits in TCON register, but there is a gap of 4
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+ * bits (one channel) after channel 0, so channels have different numbering
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+ * when accessing TCON register.
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+ *
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+ * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
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+ * in its set of bits is 2 as opposed to 3 for other channels.
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+ */
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#define TCON_START(chan) (1 << (4 * (chan) + 0))
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#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1))
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#define TCON_INVERT(chan) (1 << (4 * (chan) + 2))
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-#define TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
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+#define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
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+#define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2))
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+#define TCON_AUTORELOAD(chan) \
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+ ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
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DEFINE_SPINLOCK(samsung_pwm_lock);
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EXPORT_SYMBOL(samsung_pwm_lock);
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