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@@ -344,7 +344,7 @@ static const unsigned char init_ov9650[][3] =
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{SENSOR, OV9650_COM24, 0x00},
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/* Enable HREF and some out of spec things */
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{SENSOR, OV9650_COM12, 0x73},
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- /* Set all DBLC offset signs to positive and
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+ /* Set all DBLC offset signs to positive and
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do some out of spec stuff */
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{SENSOR, OV9650_DBLC1, 0xdf},
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{SENSOR, OV9650_COM21, 0x06},
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@@ -356,7 +356,7 @@ static const unsigned char init_ov9650[][3] =
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{SENSOR, OV9650_RSVD96, 0x04},
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/* Enable full range output */
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{SENSOR, OV9650_COM15, 0x0},
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- /* Enable HREF at optical black, enable ADBLC bias,
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+ /* Enable HREF at optical black, enable ADBLC bias,
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enable ADBLC, reset timings at format change */
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{SENSOR, OV9650_COM6, 0x4b},
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/* Subtract 32 from the B channel bias */
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@@ -377,7 +377,7 @@ static const unsigned char init_ov9650[][3] =
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{SENSOR, OV9650_AEB, 0x5c},
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/* Set the high and low limit nibbles to 3 */
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{SENSOR, OV9650_VPT, 0xc3},
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- /* Set the Automatic Gain Ceiling (AGC) to 128x,
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+ /* Set the Automatic Gain Ceiling (AGC) to 128x,
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drop VSYNC at frame drop,
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limit exposure timing,
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drop frame when the AEC step is larger than the exposure gap */
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@@ -386,9 +386,9 @@ static const unsigned char init_ov9650[][3] =
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and set PWDN to SLVS (slave mode vertical sync) */
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{SENSOR, OV9650_COM10, 0x42},
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/* Set horizontal column start high to default value */
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- {SENSOR, OV9650_HSTART, 0x1a},
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+ {SENSOR, OV9650_HSTART, 0x1a}, /* 210 */
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/* Set horizontal column end */
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- {SENSOR, OV9650_HSTOP, 0xbf},
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+ {SENSOR, OV9650_HSTOP, 0xbf}, /* 1534 */
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/* Complementing register to the two writes above */
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{SENSOR, OV9650_HREF, 0xb2},
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/* Set vertical row start high bits */
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@@ -428,11 +428,12 @@ static const unsigned char init_ov9650[][3] =
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{BRIDGE, M5602_XB_VSYNC_PARA, 0x09},
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{BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
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{BRIDGE, M5602_XB_VSYNC_PARA, 0x01},
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- {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0},
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+ {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0}, /* 480 */
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+ {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
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{BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
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{BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
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- {BRIDGE, M5602_XB_HSYNC_PARA, 0x5e},
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- {BRIDGE, M5602_XB_HSYNC_PARA, 0x02},
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+ {BRIDGE, M5602_XB_HSYNC_PARA, 0x5e}, /* 94 */
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+ {BRIDGE, M5602_XB_HSYNC_PARA, 0x02}, /* 734 */
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{BRIDGE, M5602_XB_HSYNC_PARA, 0xde}
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};
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Erik Andrén