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@@ -103,15 +103,15 @@
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#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
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#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
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#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
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-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
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-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
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-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
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-#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
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-#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
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-#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
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-#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
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+#define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
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+#define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0
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+#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
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+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
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-#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
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+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
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+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
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+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
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+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
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#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
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#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
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#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
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