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@@ -30,105 +30,112 @@
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#define I3000_MCHBAR_MASK 0xffffc000
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#define I3000_MMR_WINDOW_SIZE 16384
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-#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
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- *
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- * 7:1 reserved
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- * 0 bit 32 of address
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- */
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-#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
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- *
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- * 31:7 address
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- * 6:1 reserved
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- * 0 Error channel 0/1
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- */
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-#define I3000_DEAP_GRAIN (1 << 7)
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-#define I3000_DEAP_PFN(edeap, deap) ((((edeap) & 1) << (32 - PAGE_SHIFT)) | \
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- ((deap) >> PAGE_SHIFT))
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-#define I3000_DEAP_OFFSET(deap) ((deap) & ~(I3000_DEAP_GRAIN-1) & ~PAGE_MASK)
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+#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
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+ *
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+ * 7:1 reserved
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+ * 0 bit 32 of address
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+ */
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+#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
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+ *
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+ * 31:7 address
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+ * 6:1 reserved
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+ * 0 Error channel 0/1
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+ */
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+#define I3000_DEAP_GRAIN (1 << 7)
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+#define I3000_DEAP_PFN(edeap, deap) ((((edeap) & 1) << (32 - PAGE_SHIFT)) \
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+ | ((deap) >> PAGE_SHIFT))
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+#define I3000_DEAP_OFFSET(deap) ((deap) & ~(I3000_DEAP_GRAIN-1) & \
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+ ~PAGE_MASK)
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#define I3000_DEAP_CHANNEL(deap) ((deap) & 1)
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-#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
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- *
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- * 7:0 DRAM ECC Syndrome
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- */
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-
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-#define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
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- *
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- * 15:12 reserved
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- * 11 MCH Thermal Sensor Event for SMI/SCI/SERR
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- * 10 reserved
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- * 9 LOCK to non-DRAM Memory Flag (LCKF)
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- * 8 Received Refresh Timeout Flag (RRTOF)
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- * 7:2 reserved
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- * 1 Multiple-bit DRAM ECC Error Flag (DMERR)
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- * 0 Single-bit DRAM ECC Error Flag (DSERR)
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- */
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+#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
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+ *
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+ * 7:0 DRAM ECC Syndrome
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+ */
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+
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+#define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
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+ *
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+ * 15:12 reserved
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+ * 11 MCH Thermal Sensor Event
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+ * for SMI/SCI/SERR
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+ * 10 reserved
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+ * 9 LOCK to non-DRAM Memory Flag (LCKF)
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+ * 8 Received Refresh Timeout Flag (RRTOF)
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+ * 7:2 reserved
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+ * 1 Multi-bit DRAM ECC Error Flag (DMERR)
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+ * 0 Single-bit DRAM ECC Error Flag (DSERR)
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+ */
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#define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
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#define I3000_ERRSTS_UE 0x0002
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#define I3000_ERRSTS_CE 0x0001
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-#define I3000_ERRCMD 0xca /* Error Command (16b)
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- *
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- * 15:12 reserved
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- * 11 SERR on MCH Thermal Sensor Event (TSESERR)
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- * 10 reserved
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- * 9 SERR on LOCK to non-DRAM Memory (LCKERR)
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- * 8 SERR on DRAM Refresh Timeout (DRTOERR)
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- * 7:2 reserved
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- * 1 SERR Multiple-Bit DRAM ECC Error (DMERR)
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- * 0 SERR on Single-Bit ECC Error (DSERR)
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- */
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+#define I3000_ERRCMD 0xca /* Error Command (16b)
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+ *
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+ * 15:12 reserved
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+ * 11 SERR on MCH Thermal Sensor Event
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+ * (TSESERR)
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+ * 10 reserved
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+ * 9 SERR on LOCK to non-DRAM Memory
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+ * (LCKERR)
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+ * 8 SERR on DRAM Refresh Timeout
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+ * (DRTOERR)
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+ * 7:2 reserved
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+ * 1 SERR Multi-Bit DRAM ECC Error
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+ * (DMERR)
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+ * 0 SERR on Single-Bit ECC Error
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+ * (DSERR)
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+ */
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/* Intel MMIO register space - device 0 function 0 - MMR space */
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#define I3000_DRB_SHIFT 25 /* 32MiB grain */
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-#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
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- *
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- * 7:0 Channel 0 DRAM Rank Boundary Address
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- */
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-#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
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- *
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- * 7:0 Channel 1 DRAM Rank Boundary Address
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- */
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-
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-#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
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- *
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- * 7 reserved
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- * 6:4 DRAM odd Rank Attribute
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- * 3 reserved
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- * 2:0 DRAM even Rank Attribute
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- *
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- * Each attribute defines the page
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- * size of the corresponding rank:
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- * 000: unpopulated
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- * 001: reserved
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- * 010: 4 KB
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- * 011: 8 KB
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- * 100: 16 KB
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- * Others: reserved
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- */
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-#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
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-#define ODD_RANK_ATTRIB(dra) (((dra) & 0x70) >> 4)
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-#define EVEN_RANK_ATTRIB(dra) ((dra) & 0x07)
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-
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-#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
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- *
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- * 31:30 reserved
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- * 29 Initialization Complete (IC)
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- * 28:11 reserved
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- * 10:8 Refresh Mode Select (RMS)
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- * 7 reserved
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- * 6:4 Mode Select (SMS)
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- * 3:2 reserved
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- * 1:0 DRAM Type (DT)
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- */
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-
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-#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
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- *
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- * 31 Enhanced Addressing Enable (ENHADE)
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- * 30:0 reserved
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- */
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+#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
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+ *
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+ * 7:0 Channel 0 DRAM Rank Boundary Address
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+ */
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+#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
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+ *
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+ * 7:0 Channel 1 DRAM Rank Boundary Address
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+ */
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+
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+#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
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+ *
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+ * 7 reserved
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+ * 6:4 DRAM odd Rank Attribute
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+ * 3 reserved
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+ * 2:0 DRAM even Rank Attribute
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+ *
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+ * Each attribute defines the page
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+ * size of the corresponding rank:
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+ * 000: unpopulated
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+ * 001: reserved
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+ * 010: 4 KB
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+ * 011: 8 KB
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+ * 100: 16 KB
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+ * Others: reserved
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+ */
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+#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
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+#define ODD_RANK_ATTRIB(dra) (((dra) & 0x70) >> 4)
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+#define EVEN_RANK_ATTRIB(dra) ((dra) & 0x07)
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+
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+#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
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+ *
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+ * 31:30 reserved
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+ * 29 Initialization Complete (IC)
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+ * 28:11 reserved
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+ * 10:8 Refresh Mode Select (RMS)
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+ * 7 reserved
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+ * 6:4 Mode Select (SMS)
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+ * 3:2 reserved
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+ * 1:0 DRAM Type (DT)
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+ */
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+
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+#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
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+ *
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+ * 31 Enhanced Addressing Enable (ENHADE)
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+ * 30:0 reserved
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+ */
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enum i3000p_chips {
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I3000 = 0,
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@@ -187,7 +194,8 @@ static void i3000_get_error_info(struct mem_ctl_info *mci,
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pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
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}
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- /* Clear any error bits.
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+ /*
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+ * Clear any error bits.
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* (Yes, we really clear bits by writing 1 to them.)
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*/
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pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
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@@ -245,7 +253,8 @@ static int i3000_is_interleaved(const unsigned char *c0dra,
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{
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int i;
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- /* If the channels aren't populated identically then
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+ /*
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+ * If the channels aren't populated identically then
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* we're not interleaved.
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*/
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for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
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@@ -254,7 +263,8 @@ static int i3000_is_interleaved(const unsigned char *c0dra,
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EVEN_RANK_ATTRIB(c1dra[i]))
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return 0;
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- /* If the rank boundaries for the two channels are different
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+ /*
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+ * If the rank boundaries for the two channels are different
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* then we're not interleaved.
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*/
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for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
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@@ -300,7 +310,8 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
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iounmap(window);
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- /* Figure out how many channels we have.
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+ /*
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+ * Figure out how many channels we have.
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*
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* If we have what the datasheet calls "asymmetric channels"
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* (essentially the same as what was called "virtual single
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@@ -363,7 +374,8 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
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csrow->edac_mode = EDAC_UNKNOWN;
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}
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- /* Clear any error bits.
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+ /*
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+ * Clear any error bits.
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* (Yes, we really clear bits by writing 1 to them.)
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*/
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pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
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@@ -390,7 +402,7 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
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debugf3("MC: %s(): success\n", __func__);
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return 0;
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- fail:
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+fail:
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if (mci)
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edac_mc_free(mci);
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@@ -409,7 +421,7 @@ static int __devinit i3000_init_one(struct pci_dev *pdev,
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return -EIO;
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rc = i3000_probe1(pdev, ent->driver_data);
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- if (mci_pdev == NULL)
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+ if (!mci_pdev)
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mci_pdev = pci_dev_get(pdev);
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return rc;
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@@ -424,7 +436,8 @@ static void __devexit i3000_remove_one(struct pci_dev *pdev)
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if (i3000_pci)
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edac_pci_release_generic_ctl(i3000_pci);
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- if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
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+ mci = edac_mc_del_mc(&pdev->dev);
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+ if (!mci)
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return;
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edac_mc_free(mci);
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@@ -457,7 +470,7 @@ static int __init i3000_init(void)
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if (pci_rc < 0)
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goto fail0;
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- if (mci_pdev == NULL) {
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+ if (!mci_pdev) {
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i3000_registered = 0;
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mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_3000_HB, NULL);
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