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+/*
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+ * USB block power/access management abstraction.
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+ *
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+ * Au1000+: The OHCI block control register is at the far end of the OHCI memory
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+ * area. Au1550 has OHCI on different base address. No need to handle
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+ * UDC here.
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+ * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG
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+ * as well as the PHY for EHCI and UDC.
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+ *
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/spinlock.h>
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+#include <linux/syscore_ops.h>
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+#include <asm/mach-au1x00/au1000.h>
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+
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+/* control register offsets */
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+#define AU1000_OHCICFG 0x7fffc
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+#define AU1550_OHCICFG 0x07ffc
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+#define AU1200_USBCFG 0x04
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+
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+/* Au1000 USB block config bits */
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+#define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
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+#define USBHEN_CE (1 << 3) /* OHCI block clock enable */
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+#define USBHEN_E (1 << 2) /* OHCI block enable */
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+#define USBHEN_C (1 << 1) /* OHCI block coherency bit */
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+#define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
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+
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+/* Au1200 USB config bits */
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+#define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
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+#define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */
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+#define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */
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+#define USBCFG_SSD (1 << 23) /* serial short detect en */
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+#define USBCFG_PPE (1 << 19) /* HS PHY PLL */
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+#define USBCFG_UCE (1 << 18) /* UDC clock enable */
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+#define USBCFG_ECE (1 << 17) /* EHCI clock enable */
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+#define USBCFG_OCE (1 << 16) /* OHCI clock enable */
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+#define USBCFG_FLA(x) (((x) & 0x3f) << 8)
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+#define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */
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+#define USBCFG_GME (1 << 6) /* OTG mem access */
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+#define USBCFG_DBE (1 << 5) /* UDC busmaster enable */
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+#define USBCFG_DME (1 << 4) /* UDC mem enable */
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+#define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */
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+#define USBCFG_EME (1 << 2) /* EHCI mem enable */
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+#define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */
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+#define USBCFG_OME (1 << 0) /* OHCI mem enable */
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+#define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\
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+ USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \
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+ USBCFG_GME | USBCFG_DBE | USBCFG_DME | \
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+ USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \
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+ USBCFG_OME)
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+
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+
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+static DEFINE_SPINLOCK(alchemy_usb_lock);
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+
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+
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+static inline void __au1200_ohci_control(void __iomem *base, int enable)
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+{
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+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
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+ if (enable) {
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+ __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG);
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+ wmb();
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+ udelay(2000);
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+ } else {
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+ __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG);
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+ wmb();
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+ udelay(1000);
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+ }
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+}
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+
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+static inline void __au1200_ehci_control(void __iomem *base, int enable)
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+{
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+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
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+ if (enable) {
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+ __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG);
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+ wmb();
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+ udelay(1000);
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+ } else {
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+ if (!(r & USBCFG_UCE)) /* UDC also off? */
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+ r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
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+ __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG);
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+ wmb();
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+ udelay(1000);
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+ }
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+}
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+
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+static inline void __au1200_udc_control(void __iomem *base, int enable)
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+{
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+ unsigned long r = __raw_readl(base + AU1200_USBCFG);
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+ if (enable) {
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+ __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG);
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+ wmb();
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+ } else {
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+ if (!(r & USBCFG_ECE)) /* EHCI also off? */
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+ r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */
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+ __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG);
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+ wmb();
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+ }
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+}
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+
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+static inline int au1200_coherency_bug(void)
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+{
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+#if defined(CONFIG_DMA_COHERENT)
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+ /* Au1200 AB USB does not support coherent memory */
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+ if (!(read_c0_prid() & 0xff)) {
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+ printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
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+ printk(KERN_INFO "Au1200 USB: update your board or re-configure"
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+ " the kernel\n");
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+ return -ENODEV;
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+ }
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+#endif
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+ return 0;
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+}
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+
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+static inline int au1200_usb_control(int block, int enable)
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+{
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+ void __iomem *base =
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+ (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
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+ int ret = 0;
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+
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+ switch (block) {
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+ case ALCHEMY_USB_OHCI0:
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+ ret = au1200_coherency_bug();
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+ if (ret && enable)
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+ goto out;
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+ __au1200_ohci_control(base, enable);
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+ break;
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+ case ALCHEMY_USB_UDC0:
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+ __au1200_udc_control(base, enable);
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+ break;
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+ case ALCHEMY_USB_EHCI0:
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+ ret = au1200_coherency_bug();
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+ if (ret && enable)
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+ goto out;
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+ __au1200_ehci_control(base, enable);
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+ break;
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+ default:
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+ ret = -ENODEV;
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+ }
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+out:
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+ return ret;
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+}
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+
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+
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+/* initialize USB block(s) to a known working state */
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+static inline void au1200_usb_init(void)
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+{
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+ void __iomem *base =
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+ (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
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+ __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
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+ wmb();
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+ udelay(1000);
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+}
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+
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+static inline void au1000_usb_init(unsigned long rb, int reg)
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+{
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+ void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
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+ unsigned long r = __raw_readl(base);
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+
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+#if defined(__BIG_ENDIAN)
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+ r |= USBHEN_BE;
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+#endif
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+ r |= USBHEN_C;
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+
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+ __raw_writel(r, base);
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+ wmb();
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+ udelay(1000);
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+}
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+
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+
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+static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
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+{
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+ void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
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+ unsigned long r = __raw_readl(base + creg);
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+
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+ if (enable) {
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+ __raw_writel(r | USBHEN_CE, base + creg);
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+ wmb();
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+ udelay(1000);
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+ __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg);
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+ wmb();
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+ udelay(1000);
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+
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+ /* wait for reset complete (read reg twice: au1500 erratum) */
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+ while (__raw_readl(base + creg),
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+ !(__raw_readl(base + creg) & USBHEN_RD))
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+ udelay(1000);
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+ } else {
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+ __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
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+ wmb();
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+ }
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+}
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+
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+static inline int au1000_usb_control(int block, int enable, unsigned long rb,
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+ int creg)
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+{
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+ int ret = 0;
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+
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+ switch (block) {
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+ case ALCHEMY_USB_OHCI0:
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+ __au1xx0_ohci_control(enable, rb, creg);
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+ break;
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+ default:
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+ ret = -ENODEV;
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+ }
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+ return ret;
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+}
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+
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+/*
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+ * alchemy_usb_control - control Alchemy on-chip USB blocks
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+ * @block: USB block to target
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+ * @enable: set 1 to enable a block, 0 to disable
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+ */
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+int alchemy_usb_control(int block, int enable)
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+{
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+ unsigned long flags;
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+ int ret;
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+
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+ spin_lock_irqsave(&alchemy_usb_lock, flags);
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+ switch (alchemy_get_cputype()) {
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+ case ALCHEMY_CPU_AU1000:
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+ case ALCHEMY_CPU_AU1500:
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+ case ALCHEMY_CPU_AU1100:
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+ ret = au1000_usb_control(block, enable,
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+ AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
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+ break;
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+ case ALCHEMY_CPU_AU1550:
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+ ret = au1000_usb_control(block, enable,
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+ AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
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+ break;
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+ case ALCHEMY_CPU_AU1200:
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+ ret = au1200_usb_control(block, enable);
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+ break;
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+ default:
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+ ret = -ENODEV;
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+ }
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+ spin_unlock_irqrestore(&alchemy_usb_lock, flags);
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+ return ret;
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+}
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+EXPORT_SYMBOL_GPL(alchemy_usb_control);
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+
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+
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+static unsigned long alchemy_usb_pmdata[2];
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+
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+static void au1000_usb_pm(unsigned long br, int creg, int susp)
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+{
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+ void __iomem *base = (void __iomem *)KSEG1ADDR(br);
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+
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+ if (susp) {
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+ alchemy_usb_pmdata[0] = __raw_readl(base + creg);
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+ /* There appears to be some undocumented reset register.... */
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+ __raw_writel(0, base + 0x04);
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+ wmb();
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+ __raw_writel(0, base + creg);
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+ wmb();
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+ } else {
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+ __raw_writel(alchemy_usb_pmdata[0], base + creg);
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+ wmb();
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+ }
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+}
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+
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+static void au1200_usb_pm(int susp)
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+{
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+ void __iomem *base =
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+ (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR);
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+ if (susp) {
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+ /* save OTG_CAP/MUX registers which indicate port routing */
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+ /* FIXME: write an OTG driver to do that */
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+ alchemy_usb_pmdata[0] = __raw_readl(base + 0x00);
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+ alchemy_usb_pmdata[1] = __raw_readl(base + 0x04);
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+ } else {
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+ /* restore access to all MMIO areas */
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+ au1200_usb_init();
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+
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+ /* restore OTG_CAP/MUX registers */
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+ __raw_writel(alchemy_usb_pmdata[0], base + 0x00);
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+ __raw_writel(alchemy_usb_pmdata[1], base + 0x04);
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+ wmb();
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+ }
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+}
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+
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+static void alchemy_usb_pm(int susp)
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+{
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+ switch (alchemy_get_cputype()) {
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+ case ALCHEMY_CPU_AU1000:
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+ case ALCHEMY_CPU_AU1500:
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+ case ALCHEMY_CPU_AU1100:
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+ au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp);
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+ break;
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+ case ALCHEMY_CPU_AU1550:
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+ au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp);
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+ break;
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+ case ALCHEMY_CPU_AU1200:
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+ au1200_usb_pm(susp);
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+ break;
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+ }
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+}
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+
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+static int alchemy_usb_suspend(void)
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+{
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+ alchemy_usb_pm(1);
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+ return 0;
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+}
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+
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+static void alchemy_usb_resume(void)
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+{
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+ alchemy_usb_pm(0);
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+}
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+
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+static struct syscore_ops alchemy_usb_pm_ops = {
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+ .suspend = alchemy_usb_suspend,
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+ .resume = alchemy_usb_resume,
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+};
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+
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+static int __init alchemy_usb_init(void)
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+{
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+ switch (alchemy_get_cputype()) {
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+ case ALCHEMY_CPU_AU1000:
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+ case ALCHEMY_CPU_AU1500:
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+ case ALCHEMY_CPU_AU1100:
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+ au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
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+ break;
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+ case ALCHEMY_CPU_AU1550:
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+ au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
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+ break;
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+ case ALCHEMY_CPU_AU1200:
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+ au1200_usb_init();
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+ break;
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+ }
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+
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+ register_syscore_ops(&alchemy_usb_pm_ops);
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+
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+ return 0;
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+}
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+arch_initcall(alchemy_usb_init);
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Manuel Lauss