|
@@ -70,7 +70,7 @@
|
|
struct omap_dm_timer {
|
|
struct omap_dm_timer {
|
|
unsigned long phys_base;
|
|
unsigned long phys_base;
|
|
int irq;
|
|
int irq;
|
|
-#ifdef CONFIG_ARCH_OMAP2
|
|
|
|
|
|
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
struct clk *iclk, *fclk;
|
|
struct clk *iclk, *fclk;
|
|
#endif
|
|
#endif
|
|
void __iomem *io_base;
|
|
void __iomem *io_base;
|
|
@@ -85,6 +85,9 @@ struct omap_dm_timer {
|
|
#define omap2_dm_timers NULL
|
|
#define omap2_dm_timers NULL
|
|
#define omap2_dm_source_names NULL
|
|
#define omap2_dm_source_names NULL
|
|
#define omap2_dm_source_clocks NULL
|
|
#define omap2_dm_source_clocks NULL
|
|
|
|
+#define omap3_dm_timers NULL
|
|
|
|
+#define omap3_dm_source_names NULL
|
|
|
|
+#define omap3_dm_source_clocks NULL
|
|
|
|
|
|
static struct omap_dm_timer omap1_dm_timers[] = {
|
|
static struct omap_dm_timer omap1_dm_timers[] = {
|
|
{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
|
|
{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
|
|
@@ -104,6 +107,9 @@ static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
|
|
#define omap_dm_clk_enable(x) clk_enable(x)
|
|
#define omap_dm_clk_enable(x) clk_enable(x)
|
|
#define omap_dm_clk_disable(x) clk_disable(x)
|
|
#define omap_dm_clk_disable(x) clk_disable(x)
|
|
#define omap1_dm_timers NULL
|
|
#define omap1_dm_timers NULL
|
|
|
|
+#define omap3_dm_timers NULL
|
|
|
|
+#define omap3_dm_source_names NULL
|
|
|
|
+#define omap3_dm_source_clocks NULL
|
|
|
|
|
|
static struct omap_dm_timer omap2_dm_timers[] = {
|
|
static struct omap_dm_timer omap2_dm_timers[] = {
|
|
{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
|
|
{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
|
|
@@ -130,6 +136,39 @@ static const char *omap2_dm_source_names[] __initdata = {
|
|
static struct clk **omap2_dm_source_clocks[3];
|
|
static struct clk **omap2_dm_source_clocks[3];
|
|
static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
|
|
static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
|
|
|
|
|
|
|
|
+#elif defined(CONFIG_ARCH_OMAP3)
|
|
|
|
+
|
|
|
|
+#define omap_dm_clk_enable(x) clk_enable(x)
|
|
|
|
+#define omap_dm_clk_disable(x) clk_disable(x)
|
|
|
|
+#define omap1_dm_timers NULL
|
|
|
|
+#define omap2_dm_timers NULL
|
|
|
|
+#define omap2_dm_source_names NULL
|
|
|
|
+#define omap2_dm_source_clocks NULL
|
|
|
|
+
|
|
|
|
+static struct omap_dm_timer omap3_dm_timers[] = {
|
|
|
|
+ { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
|
|
|
|
+ { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
|
|
|
|
+ { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
|
|
|
|
+ { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
|
|
|
|
+ { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
|
|
|
|
+ { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
|
|
|
|
+ { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
|
|
|
|
+ { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
|
|
|
|
+ { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
|
|
|
|
+ { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
|
|
|
|
+ { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
|
|
|
|
+ { .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static const char *omap3_dm_source_names[] __initdata = {
|
|
|
|
+ "sys_ck",
|
|
|
|
+ "omap_32k_fck",
|
|
|
|
+ NULL
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct clk **omap3_dm_source_clocks[2];
|
|
|
|
+static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
|
|
|
|
+
|
|
#else
|
|
#else
|
|
|
|
|
|
#error OMAP architecture not supported!
|
|
#error OMAP architecture not supported!
|
|
@@ -310,7 +349,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
|
|
return inputmask;
|
|
return inputmask;
|
|
}
|
|
}
|
|
|
|
|
|
-#elif defined(CONFIG_ARCH_OMAP2)
|
|
|
|
|
|
+#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
|
|
|
|
|
|
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
|
|
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
|
|
{
|
|
{
|
|
@@ -502,7 +541,7 @@ int __init omap_dm_timer_init(void)
|
|
struct omap_dm_timer *timer;
|
|
struct omap_dm_timer *timer;
|
|
int i;
|
|
int i;
|
|
|
|
|
|
- if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
|
|
|
|
|
|
+ if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
|
|
return -ENODEV;
|
|
return -ENODEV;
|
|
|
|
|
|
spin_lock_init(&dm_timer_lock);
|
|
spin_lock_init(&dm_timer_lock);
|
|
@@ -513,6 +552,10 @@ int __init omap_dm_timer_init(void)
|
|
dm_timers = omap2_dm_timers;
|
|
dm_timers = omap2_dm_timers;
|
|
dm_source_names = (char **)omap2_dm_source_names;
|
|
dm_source_names = (char **)omap2_dm_source_names;
|
|
dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
|
|
dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
|
|
|
|
+ } else if (cpu_is_omap34xx()) {
|
|
|
|
+ dm_timers = omap3_dm_timers;
|
|
|
|
+ dm_source_names = (char **)omap3_dm_source_names;
|
|
|
|
+ dm_source_clocks = (struct clk **)omap3_dm_source_clocks;
|
|
}
|
|
}
|
|
|
|
|
|
if (cpu_class_is_omap2())
|
|
if (cpu_class_is_omap2())
|
|
@@ -525,7 +568,7 @@ int __init omap_dm_timer_init(void)
|
|
for (i = 0; i < dm_timer_count; i++) {
|
|
for (i = 0; i < dm_timer_count; i++) {
|
|
timer = &dm_timers[i];
|
|
timer = &dm_timers[i];
|
|
timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
|
|
timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
|
|
-#ifdef CONFIG_ARCH_OMAP2
|
|
|
|
|
|
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
if (cpu_class_is_omap2()) {
|
|
if (cpu_class_is_omap2()) {
|
|
char clk_name[16];
|
|
char clk_name[16];
|
|
sprintf(clk_name, "gpt%d_ick", i + 1);
|
|
sprintf(clk_name, "gpt%d_ick", i + 1);
|