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@@ -230,13 +230,11 @@ enum {
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#define XRDYEN BIT(10)
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#define XEMPTYEOFEN BIT(14)
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-/* CLKR signal muxing options */
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-#define CLKR_SRC_CLKR 0
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-#define CLKR_SRC_CLKX 1
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-
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-/* FSR signal muxing options */
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-#define FSR_SRC_FSR 0
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-#define FSR_SRC_FSX 1
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+/* Clock signal muxing options */
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+#define CLKR_SRC_CLKR 0 /* CLKR signal is from the CLKR pin */
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+#define CLKR_SRC_CLKX 1 /* CLKR signal is from the CLKX pin */
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+#define FSR_SRC_FSR 2 /* FSR signal is from the FSR pin */
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+#define FSR_SRC_FSX 3 /* FSR signal is from the FSX pin */
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/* McBSP functional clock sources */
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#define MCBSP_CLKS_PRCM_SRC 0
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@@ -333,8 +331,7 @@ void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx);
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int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id);
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/* McBSP signal muxing API */
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-void omap2_mcbsp1_mux_clkr_src(struct omap_mcbsp *mcbsp, u8 mux);
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-void omap2_mcbsp1_mux_fsr_src(struct omap_mcbsp *mcbsp, u8 mux);
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+int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux);
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/* Sidetone specific API */
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int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain);
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