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@@ -65,7 +65,14 @@ static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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u8 reg = stmpe->regs[which] - (offset / 8);
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u8 mask = 1 << (offset % 8);
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- stmpe_reg_write(stmpe, reg, mask);
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+ /*
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+ * Some variants have single register for gpio set/clear functionality.
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+ * For them we need to write 0 to clear and 1 to set.
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+ */
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+ if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
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+ stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
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+ else
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+ stmpe_reg_write(stmpe, reg, mask);
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}
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static int stmpe_gpio_direction_output(struct gpio_chip *chip,
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@@ -132,6 +139,10 @@ static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
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return -EINVAL;
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+ /* STMPE801 doesn't have RE and FE registers */
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+ if (stmpe_gpio->stmpe->partnum == STMPE801)
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+ return 0;
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+
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if (type == IRQ_TYPE_EDGE_RISING)
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stmpe_gpio->regs[REG_RE][regoffset] |= mask;
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else
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@@ -165,6 +176,11 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
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int i, j;
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for (i = 0; i < CACHE_NR_REGS; i++) {
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+ /* STMPE801 doesn't have RE and FE registers */
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+ if ((stmpe->partnum == STMPE801) &&
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+ (i != REG_IE))
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+ continue;
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+
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for (j = 0; j < num_banks; j++) {
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u8 old = stmpe_gpio->oldregs[i][j];
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u8 new = stmpe_gpio->regs[i][j];
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@@ -241,8 +257,11 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
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}
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stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
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- stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
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- status[i]);
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+
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+ /* Edge detect register is not present on 801 */
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+ if (stmpe->partnum != STMPE801)
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+ stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
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+ + i, status[i]);
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}
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return IRQ_HANDLED;
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