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@@ -46,24 +46,24 @@
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#define ICTLR_COP_IER_CLR 0x38
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#define ICTLR_COP_IEP_CLASS 0x3c
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-static void (*gic_mask_irq)(struct irq_data *d);
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-static void (*gic_unmask_irq)(struct irq_data *d);
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+static void (*tegra_gic_mask_irq)(struct irq_data *d);
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+static void (*tegra_gic_unmask_irq)(struct irq_data *d);
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-#define irq_to_ictlr(irq) (((irq)-32) >> 5)
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+#define irq_to_ictlr(irq) (((irq) - 32) >> 5)
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static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE);
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-#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr)*0x100)
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+#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr) * 0x100)
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static void tegra_mask(struct irq_data *d)
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{
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void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
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- gic_mask_irq(d);
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- writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_CLR);
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+ tegra_gic_mask_irq(d);
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+ writel(1 << (d->irq & 31), addr+ICTLR_CPU_IER_CLR);
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}
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static void tegra_unmask(struct irq_data *d)
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{
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void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
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- gic_unmask_irq(d);
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+ tegra_gic_unmask_irq(d);
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writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET);
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}
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@@ -98,8 +98,8 @@ void __init tegra_init_irq(void)
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IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
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gic = get_irq_chip(29);
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- gic_unmask_irq = gic->irq_unmask;
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- gic_mask_irq = gic->irq_mask;
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+ tegra_gic_unmask_irq = gic->irq_unmask;
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+ tegra_gic_mask_irq = gic->irq_mask;
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tegra_irq.irq_ack = gic->irq_ack;
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#ifdef CONFIG_SMP
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tegra_irq.irq_set_affinity = gic->irq_set_affinity;
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