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@@ -4626,8 +4626,8 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
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val |= PIPE_12BPC;
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break;
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default:
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- val |= PIPE_8BPC;
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- break;
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+ /* Case prevented by intel_choose_pipe_bpp_dither. */
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+ BUG();
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}
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val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
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@@ -4728,7 +4728,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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struct fdi_m_n m_n = {0};
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u32 temp;
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int target_clock, pixel_multiplier, lane, link_bw, factor;
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- unsigned int pipe_bpp;
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bool dither;
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bool is_cpu_edp = false, is_pch_edp = false;
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@@ -4802,18 +4801,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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target_clock = adjusted_mode->clock;
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/* determine panel color depth */
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- dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
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+ dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
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if (is_lvds && dev_priv->lvds_dither)
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dither = true;
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- if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
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- pipe_bpp != 36) {
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- WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
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- pipe_bpp);
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- pipe_bpp = 24;
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- }
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- intel_crtc->bpp = pipe_bpp;
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-
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if (!lane) {
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/*
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* Account for spread spectrum to avoid
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