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@@ -124,6 +124,10 @@ extern int opal_enter_rtas(struct rtas_args *args,
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#define OPAL_PCI_POLL 62
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#define OPAL_PCI_MSI_EOI 63
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#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
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+#define OPAL_XSCOM_READ 65
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+#define OPAL_XSCOM_WRITE 66
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+#define OPAL_LPC_READ 67
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+#define OPAL_LPC_WRITE 68
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#ifndef __ASSEMBLY__
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@@ -337,6 +341,17 @@ enum OpalEpowStatus {
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OPAL_EPOW_OVER_INTERNAL_TEMP = 3
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};
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+/*
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+ * Address cycle types for LPC accesses. These also correspond
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+ * to the content of the first cell of the "reg" property for
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+ * device nodes on the LPC bus
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+ */
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+enum OpalLPCAddressType {
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+ OPAL_LPC_MEM = 0,
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+ OPAL_LPC_IO = 1,
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+ OPAL_LPC_FW = 2,
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+};
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+
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struct opal_machine_check_event {
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enum OpalMCE_Version version:8; /* 0x00 */
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uint8_t in_use; /* 0x01 */
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@@ -632,6 +647,14 @@ int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
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uint16_t *pci_error_type, uint16_t *severity);
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int64_t opal_pci_poll(uint64_t phb_id);
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+int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val);
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+int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val);
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+
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+int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
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+ uint32_t addr, uint32_t data, uint32_t sz);
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+int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
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+ uint32_t addr, uint32_t *data, uint32_t sz);
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+
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/* Internal functions */
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extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
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