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@@ -0,0 +1,88 @@
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+#
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+# DSP Bridge Driver Support
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+#
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+
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+menuconfig TIDSPBRIDGE
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+ tristate "DSP Bridge driver"
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+ depends on ARCH_OMAP3
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+ select OMAP_MBOX_FWK
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+ help
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+ DSP/BIOS Bridge is designed for platforms that contain a GPP and
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+ one or more attached DSPs. The GPP is considered the master or
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+ "host" processor, and the attached DSPs are processing resources
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+ that can be utilized by applications and drivers running on the GPP.
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+
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+ This driver depends on OMAP Mailbox (OMAP_MBOX_FWK).
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+
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+config BRIDGE_DVFS
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+ bool "Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)"
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+ depends on TIDSPBRIDGE && OMAP_PM_SRF && CPU_FREQ
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+ default n
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+ help
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+ DVFS allows DSP Bridge to initiate the operating point change to
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+ scale the chip voltage and frequency in order to match the
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+ performance and power consumption to the current processing
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+ requirements.
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+
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+config BRIDGE_MEMPOOL_SIZE
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+ hex "Physical memory pool size (Byte)"
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+ depends on TIDSPBRIDGE
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+ default 0x600000
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+ help
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+ Allocate specified size of memory at booting time to avoid allocation
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+ failure under heavy memory fragmentation after some use time.
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+
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+config BRIDGE_DEBUG
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+ bool "DSP Bridge Debug Support"
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+ depends on TIDSPBRIDGE
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+ help
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+ Say Y to enable Bridge debugging capabilities
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+
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+config BRIDGE_RECOVERY
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+ bool "DSP Recovery Support"
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+ depends on TIDSPBRIDGE
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+ help
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+ In case of DSP fatal error, BRIDGE driver will try to
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+ recover itself.
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+
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+config BRIDGE_CACHE_LINE_CHECK
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+ bool "Check buffers to be 128 byte aligned"
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+ depends on TIDSPBRIDGE
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+ default n
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+ help
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+ When the DSP processes data, the DSP cache controller loads 128-Byte
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+ chunks (lines) from SDRAM and writes the data back in 128-Byte chunks.
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+ If a DMM buffer does not start and end on a 128-Byte boundary, the data
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+ preceding the start address (SA) from the 128-Byte boundary to the SA
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+ and the data at addresses trailing the end address (EA) from the EA to
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+ the next 128-Byte boundary will be loaded and written back as well.
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+ This can lead to heap corruption. Say Y, to enforce the check for 128
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+ byte alignment, buffers failing this check will be rejected.
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+
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+config BRIDGE_WDT3
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+ bool "Enable WDT3 interruptions"
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+ depends on TIDSPBRIDGE
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+ default n
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+ help
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+ WTD3 is managed by DSP and once it is enabled, DSP side bridge is in
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+ charge of refreshing the timer before overflow, if the DSP hangs MPU
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+ will caught the interrupt and try to recover DSP.
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+
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+config WDT_TIMEOUT
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+ int "DSP watchdog timer timeout (in secs)"
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+ depends on BRIDGE_WDT3
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+ default 5
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+ help
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+ Watchdog timer timeout value, after that time if the watchdog timer
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+ counter is not reset the wdt overflow interrupt will be triggered
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+
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+comment "Bridge Notifications"
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+ depends on TIDSPBRIDGE
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+
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+config BRIDGE_NTFY_PWRERR
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+ bool "Notify DSP Power Error"
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+ depends on TIDSPBRIDGE
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+ help
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+ Enable notifications to registered clients on the event of power errror
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+ trying to suspend bridge driver. Say Y, to signal this event as a fatal
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+ error, this will require a bridge restart to recover.
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