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@@ -14,9 +14,7 @@
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#include <asm/arch/map.h>
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#include <asm/arch/regs-gpio.h>
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-
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#include <asm/plat-s3c/regs-serial.h>
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-#include <asm/plat-s3c/debug-macro.S>
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#define S3C2410_UART1_OFF (0x4000)
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#define SHIFT_2440TXF (14-9)
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@@ -31,7 +29,7 @@
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#endif
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.endm
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- .macro fifo_full rd, rx
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+ .macro fifo_full_s3c24xx rd, rx
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@ check for arm920 vs arm926. currently assume all arm926
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@ devices have an 64 byte FIFO identical to the s3c2440
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mrc p15, 0, \rd, c0, c0
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@@ -52,7 +50,14 @@
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tst \rd, #S3C2410_UFSTAT_TXFULL
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.endm
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- .macro fifo_level rd, rx
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+ .macro fifo_full_s3c2410 rd, rx
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+ ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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+ tst \rd, #S3C2410_UFSTAT_TXFULL
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+ .endm
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+
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+/* fifo level reading */
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+
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+ .macro fifo_level_s3c24xx rd, rx
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mrc p15, 0, \rd, c1, c0
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tst \rd, #1
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addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
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@@ -66,3 +71,27 @@
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andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
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andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
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.endm
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+
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+ .macro fifo_level_s3c2410 rd, rx
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+ ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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+ and \rd, \rd, #S3C2410_UFSTAT_TXMASK
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+ .endm
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+
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+/* Select the correct implementation depending on the configuration. The
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+ * S3C2440 will get selected by default, as these are the most widely
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+ * used variants of these
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+*/
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+
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+#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
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+#define fifo_full fifo_full_s3c2410
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+#define fifo_level fifo_level_s3c2410
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+#warning 2410only
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+#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
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+#define fifo_full fifo_full_s3c24xx
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+#define fifo_level fifo_level_s3c24xx
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+#warning generic
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+#endif
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+
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+/* include the reset of the code which will do the work */
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+
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+#include <asm/plat-s3c/debug-macro.S>
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