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@@ -234,7 +234,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
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static bool
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intel_dp_adjust_dithering(struct intel_dp *intel_dp,
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struct drm_display_mode *mode,
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- struct drm_display_mode *adjusted_mode)
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+ bool adjust_mode)
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{
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int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
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int max_lanes = intel_dp_max_lane_count(intel_dp);
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@@ -248,8 +248,8 @@ intel_dp_adjust_dithering(struct intel_dp *intel_dp,
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if (mode_rate > max_rate)
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return false;
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- if (adjusted_mode)
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- adjusted_mode->private_flags
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+ if (adjust_mode)
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+ mode->private_flags
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|= INTEL_MODE_DP_FORCE_6BPC;
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return true;
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@@ -272,7 +272,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
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return MODE_PANEL;
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}
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- if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
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+ if (!intel_dp_adjust_dithering(intel_dp, mode, false))
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return MODE_CLOCK_HIGH;
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if (mode->clock < 10000)
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@@ -712,14 +712,14 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
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mode, adjusted_mode);
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}
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- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
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+ if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
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return false;
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DRM_DEBUG_KMS("DP link computation with max lane count %i "
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"max bw %02x pixel clock %iKHz\n",
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max_lane_count, bws[max_clock], adjusted_mode->clock);
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- if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, adjusted_mode))
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+ if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
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return false;
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bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
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