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@@ -38,8 +38,8 @@ ENTRY(cpu_arm7_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r0] @ read arm instruction
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- tst r8, #1 << 20 @ L = 1 -> write?
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- orreq r1, r1, #1 << 8 @ yes.
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+ tst r8, #1 << 20 @ L = 0 -> write?
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+ orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #15 << 24
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add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
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nop
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@@ -71,8 +71,8 @@ ENTRY(cpu_arm6_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r2] @ read arm instruction
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- tst r8, #1 << 20 @ L = 1 -> write?
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- orreq r1, r1, #1 << 8 @ yes.
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+ tst r8, #1 << 20 @ L = 0 -> write?
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+ orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #14 << 24
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teq r7, #8 << 24 @ was it ldm/stm
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movne pc, lr
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